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ABSTRACT

Double patterning lithography (DPL) is considered as a most likely solution for 32nm/22nm technology. In DPL, the layout patterns are decomposed into two masks (colors). Two features (polygons) have to be assigned opposite colors if their spacing is less than certain minimum coloring distance. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may be split into two parts to resolve the conflict but the resulting stitch causes yield loss due to overlay error and increases manufacturing cost. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose an algorithm to minimize the number of conflicts and stitches simultaneously. Our algorithm is based on grid layout model and integer linear programming. Two techniques, independent component computation and layout partition, are proposed to reduce runtime of the algorithm. The experimental results show that, compared with the two phase decomposition flow, the proposed algorithm reduces the conflicts significantly using less stitches under reasonable runtime.

REFERENCES

• 1: Micrea Dusa, Jo Finders, and Stephen Hsu. Double patterning lithography: The bridge between low k1 arf and euv. In Microlithography World, Feb 2008.
• 2: George E. Bailey, Alexander Tritchkov, Jea-Woo Park, Le Hong, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Peng Xie, and Janko Versluijs. Double pattern EDA solutions for 32nm HP and beyond. In Proc. SPIE 6521, 2007.
• 3: V. Wiaux, S. Verhaegen, S. Cheng, F. Iwamoto, P. Jaenen, M. Maenhoudt, T. Matsuda, S. Postnikov, and G. Vandenberghe. Split and design guidelines for double patterning. In Proc. of SPIE, volume 6924, 2008.
• 4: A. B. Kahng. Key Directions and a Roadmap for Electrical Design for Manufacturability. In Proc. European Solid-State Circuits Conf, 2007.
• 5: M. Drapeau, V. Wiaux, E .Hendrickx, S. Verhaegen, and T. Machida. Double patterning design split implementation and validation for the 32nm node. In Proc. of SPIE, volume 6521, 2007.
• 6: Tsann-Bim Chiou, Robert Socha, Hong Chen, Luoqi Chen, Stephen Hsu, Peter Nikolsky, Anton van Oosten, and Alek C. Chen. Development of layout split algorithms and printability evaluation for double patterning technology. In Proc. of SPIE, March 2008.
• 7: Andrew B. Kahng , Chul-Hong Park , Xu Xu , Hailong Yao, Layout decomposition for double patterning lithography, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
• 8: http://www.gnu.org/software/glpk/glpk.html.
• 9: http://glaros.dtc.umn.edu/gkhome/views/metis.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design

Keywords:
double patterning lithography, integer linear programming, layout decomposition