Take a look at the new version of this page: [ beta version ]. Tell us what you think.

ABSTRACT

Enormous technical and economic challenges facing technology scaling has rendered strain engineering techniques as the critical enabler of high performance designs in sub-$100$nm geometries. One of these techniques, source/drain (S/D) SiGe, has an interesting property that the mobility of the device is dependent on the size of active area (AA) surrounding it. To exploit this phenomenon for higher performance, a circuit designer needs first order and computationally tractable transistor level models. This paper provides the first AA sizing dependent RC switch level model of a logic gate which can be readily used by circuit designers. We derive the methodology to optimally use AA sizing for some common cells such as NAND, NOR and INV. For the first time, we formulate a convex optimization problem for concurrent AA and gate sizing problem for performance optimization and solve it optimally. We also analytically solve AA sizing aware optimal repeater insertion problem for dealing with the menace of long global interconnects in modern chip design. Experimental results demonstrate that our methodology can reduce inter-chip long global interconnect delay by 9% and inter-module gate delays by 10% with only 11% increase in dynamic power dissipation.

REFERENCES

• 1: Ashutosh Chakraborty , Sean X. Shi , David Z. Pan, Layout level timing optimization by leveraging active area dependent mobility of strained-silicon devices, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany [doi>10.1145/1403375.1403582]
• 2: L. Washington et al., "pMOSFET with 200% mobility enhancement induced by multiple stressors," Electron Device Letters, IEEE, vol. 27, no. 6, pp. 511--513, June 2006.
• 3: G. Eneman et al., "Scalability of the si_1-χge_χx source/drain technology for the 45-nm technology node and beyond," in IEEE Transactions on Electron Devices, vol. 53, July 2006.
• 4: Y.-C. Yeo et al., "Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium," Electron Devices Meeting, 2000. IEDM Technical Digest. International, pp. 753--756, 2000.
• 5: W.-S. Liao et al., "Pmos hole mobility enhancement through SiGe conductive channel and highly compressive ild-hboxSiN_χx stressing layer," Electron Device Letters, IEEE, vol. 29, no. 1, pp. 86--88, Jan. 2008.
• 6: H. Yang et al., "Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing," IEDM Technical Digest, pp. 1075--1077, Dec. 2004.
• 7: Vivek Joshi , Brian Cline , Dennis Sylvester , David Blaauw , Kanak Agarwal, Stress aware layout optimization, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA [doi>10.1145/1353629.1353666]
• 8: Lithography Report, pp 17. http://www.itrs.net/Links/2007ITRS/2007_Chapters.
• 9: G. Sun et al., "Hole Mobility in Silicon Inversion Layers: Stress and Surface Orientation," Journal of Applied Physics, vol. 102, no. 8, p. 084501, 2007.
• 10: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 11: IWLS 1991 LGSynth Benchmarks. http://www.cbl.ncsu.edu/benchmarks/LGSynth91.
• 12: E. Sentovich et al., "Sis: A system for sequential circuit synthesis," Tech. Rep. UCB/ERL M92/41, EECS Department, University of California, Berkeley, 1992.
• 13: R. Fourer et al., The AMPL Book. http://www.ampl.com, 2nd ed., 2002.
• 14: MOSEK Optimization Tool Manual. http://www.mosek.com.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.0 General

General Terms:
Design, Performance

Keywords:
buffer, performance, repeater, sizing, stress