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A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems
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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Emerging technologies table of contents
Pages 847-852  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Charles Augustine  Purdue University, West Lafayette, IN
Behtash Behin-Aein  Purdue University, West Lafayette, IN
Xuanyao Fong  Purdue University, West Lafayette, IN
Kaushik Roy  Purdue University, West Lafayette, IN
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 8,   Downloads (12 Months): 62,   Citation Count: 0
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ABSTRACT

CMOS device scaling is facing a daunting challenge with increased parameter variations and exponentially higher leakage current every new technology generation. Thus, researchers have started looking at alternative technologies. Magnetic Quantum Cellular Automata (MQCA) is such an alternative with switching energy close to thermal limits and scalability down to 5nm. In this paper, we present a circuit/architecture design methodology using MQCA. Novel clocking techniques and strategies are developed to improve computation robustness of MQCA systems. We also developed an integrated device/circuit/system compatible simulation framework to evaluate the functionality and the architecture of an MQCA based system and conducted a feasibility/comparison study to determine the effectiveness of MQCAs in digital electronics. Simulation results of an 8-bit MQCA-based Discrete Cosine Transform (DCT) with novel clocking and architecture show up to 290X and 46X improvement (at iso-delay and optimistic assumption) over 45nm CMOS in energy consumption and area, respectively.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Charles Augustine: colleagues
Behtash Behin-Aein: colleagues
Xuanyao Fong: colleagues
Kaushik Roy: colleagues