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A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories
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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Emerging technologies table of contents
Pages 835-840  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
M. Haykel Ben Jamaa  Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland
David Atienza  Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland and Complutense University of Madrid, Spain
Yusuf Leblebici  Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Giovanni De Micheli  Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 17,   Citation Count: 0
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ABSTRACT

The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correct operation. In particular, the variability affecting the decoder is expected to make very complex the test of these new devices. In this paper we present a method to simplify the test of these new devices by using a current thresholder to detect badly addressed nanowires. In the proposed method, the thresholder design is based on a stochastic and perturbative model of the current through the nanowires. Thus, the calculated thresholder parameters are robust against technology variation. As our experimental results indicate, the thresholder error probability is initially only ~ 10-4, which can be also reduced further (up to ~ 60x) by trading-off only ~ 35% area overhead in the memory.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
M. Haykel Ben Jamaa: colleagues
David Atienza: colleagues
Yusuf Leblebici: colleagues
Giovanni De Micheli: colleagues