Energy-aware register file re-partitioning for clustered VLIW architectures

ABSTRACT

VLIW architectures have gained acceptance in embedded systems. Traditional monolithic register file is not suitable for VLIW architectures with a large number of functional units. Clustered VLIW architecture is often applied, where the register file is partitioned into a number of smaller regeister files. Register files represent a substantial portion of the energy consumption in modern processors, and it is growing rapidly with wider instruction width. Most of the known clustered VLIW architectures partition the register file evenly among clusters. In this paper, we study the effect of energy consumption with register file re-partitioning on clustered VLIW architecture, where register files are not necessarily partitioned evenly. We present algorithms to compute energy-efficient re-partition of register files under different conditions. The impact of different intercluster communication models as well as the impact of program behavior on the register file re-partitioning are analyzed in this paper. Experimental results show that energy saving can be achieved using the proposed techniques.

REFERENCES

• 1: Keith I. Farkas , Paul Chow , Norman P. Jouppi , Zvonko Vranesic, The multicluster architecture: reducing cycle time through partitioning, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.149-159, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 2: Joseph A. Fisher , Paolo Faraboschi , Giuseppe Desoli, Custom-fit processors: letting applications define architectures, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.324-335, December 02-04, 1996, Paris, France
• 3: Harold N. Gabow, An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs, Journal of the ACM (JACM), v.23 n.2, p.221-234, April 1976 [doi>10.1145/321941.321942]
• 4: Magnús M. Halldórsson , Barun Chandra, Greedy local improvement and weighted set packing approximation, Journal of Algorithms, v.39 n.2, p.223-240, May 2001 [doi>10.1006/jagm.2000.1155]
• 5: http://www.ti.com/. TI TMS320C64xx DSPs.
• 6: Erik Nystrom , Alexandre E. Eichenberger, Effective cluster assignment for modulo scheduling, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.103-114, November 1998, Dallas, Texas, United States
• 7: Jesús Sánchez , Antonio González, Modulo scheduling for a fully-distributed clustered VLIW architecture, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.124-133, December 2000, Monterey, California, United States [doi>10.1145/360128.360142]
• 8: S. Sudharasanan and P. Sriam. Image and video processing using majc 5200. Intl. Conf. on Image Processing, 2000.
• 9: Andrei Terechko , Erwan Le Thenaff , Manish Garg , Jos van Eijndhoven , Henk Corporaal, Inter-Cluster Communication Models for Clustered VLIW Processors, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.354, February 08-12, 2003
• 10: V. Zyuban , P. Kogge, The energy complexity of register files, Proceedings of the 1998 international symposium on Low power electronics and design, p.305-310, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280943]
• 11: Victor V. Zyuban , Peter M. Kogge, Inherently Lower-Power High-Performance Superscalar Architectures, IEEE Transactions on Computers, v.50 n.3, p.268-285, March 2001 [doi>10.1109/12.910816]