| Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Yokohama, Japan
SESSION: Verification, test, and yield
table of contents
Pages 769-774
Year of Publication: 2009
ISBN:978-1-4244-2748-2
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IEEE Press
Piscataway, NJ, USA
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ABSTRACT
Constrained random stimulus generation plays significant roles in hardware verification nowadays, and the quality of the generated stimuli is key to the efficiency of the test process. In this work, we present a linear dynamic method to guide random stimulus generation by SAT solvers. A splitting simplified Min-Distance-Sum evaluation method and an XOR sampling strategy are integrated in the self-adjusting random stimulus generation framework. The evenness of the split groups is evaluated to find out some uneven parts. Then, random partial solutions for the uneven parts and random XOR constraints for the other inputs are added into constraints to get better distributed stimuli. Experimental results show that our method can evaluate the evenness as well as more complex formulae for stimulus generation, and also confirm that the self-adjusting method can improve the fault coverage ratio by more than 17% averagely with the same number of stimuli.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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Synopsys Inc., "Constrained-random test generation and functional coverage with Vera," Technical report, Feb. 2003.
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2
|
L. Singh, L. Drucker, "Advanced Verification Techniques: A SystemC Based Approach for Successful Tapeout," Springer US, 2004.
|
| |
3
|
SystemC Verification Working Group, "Systemc verification standard specification," OSCI website: http://www.systemc.org, May. 2003.
|
| |
4
|
J. Yuan, A. Aziz, C. Pixley, K. Albin, "Simplifying Boolean constraint solving for random simulation-vector generation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 3, pp. 412--420, 2004.
|
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5
|
|
| |
6
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|
 |
7
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Matthew W. Moskewicz , Conor F. Madigan , Ying Zhao , Lintao Zhang , Sharad Malik, Chaff: engineering an efficient SAT solver, Proceedings of the 38th conference on Design automation, p.530-535, June 2001, Las Vegas, Nevada, United States
[doi> 10.1145/378239.379017]
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8
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N. Eén and N. Sörensson, "An extensible SAT solver," International Conference on Theory and Applications of Satisfiability Testing, pp. 502--518, 2003.
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9
|
|
| |
10
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C. P. Gomes, A. Sabharwal, B. Selman, "Near-Uniform Sampling of Combinatorial Spaces Using XOR Constraints," the 20th Annual Conference on Neural Information Processing Systems, pp. 481--488, Dec 2006.
|
| |
11
|
C. P. Gomes, W. Hoeve, A. Sabharwal, B. Selman, "Counting CSP Solutions Using Generalized XOR Constraints," the 22nd Conference on Artificial Intelligence, pp. 204--209, July 2007.
|
 |
12
|
|
 |
13
|
|
| |
14
|
A. J. Compton, "An Algorithm for the Even Distribution of Entities in One Dimension," the Computer Journal, Vol. 28, No. 5, pp. 530--537, 1985.
|
| |
15
|
H. K. Lee and D. S. Ha, "HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 9, pp. 1048--1058, 1996.
|
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16
|
ISCAS89 Sequential Benchmark Circuits: http://www.ece.vt.edu/mhsiao/iscas89.html
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17
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