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A cycle-based synthesis algorithm for reversible logic
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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Emerging design methodologies and applications table of contents
Pages 745-750  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Zahra Sasanian  Amirkabir University of Technology, Tehran, Iran
Mehdi Saeedi  Amirkabir University of Technology, Tehran, Iran
Mehdi Sedighi  Amirkabir University of Technology, Tehran, Iran
Morteza Saheb Zamani  Amirkabir University of Technology, Tehran, Iran
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 13,   Downloads (12 Months): 37,   Citation Count: 0
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ABSTRACT

Several algorithms have been proposed for the synthesis of reversible circuits. In this paper, a cycle-based synthesis algorithm for reversible logic, based on the NCT library, has been proposed. In other words, direct implementation of a single 3-cycle, a pair of 3-cycles and a pair of 2-cycles have been explored and used to propose an efficient Toffoli-based synthesis algorithm for reversible circuits. The synthesis algorithm decomposes a given large cycle into a set of single 3-cycles, pairs of 3-cycles and pair of 2-cycles and synthesizes the resulted cycles directly. Our experimental results show that the proposed synthesis algorithm can outperform the available 2-cycle-based approach about 34% on average. In addition, several discussions for the generalization of the proposed method to the 2m-cycles are given.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. Landauer, "Irreversibility and Heat Generation in the Computing Process," IBM Journal, Vol. 5, pp. 183--191, 1961.
 
2
G. Schrom, "Ultra-Low-Power CMOS Technology," PhD Thesis, Technischen Universitat Wien, 1998.
 
3
E. Knill, R. Laamme, and G. J. Milburn, "A Scheme for Efficient Quantum Computation with Linear Optics," Nature, pp. 46--52, 2001.
 
4
 
5
 
6
V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Synthesis of Reversible Logic Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 710--722, 2003.
 
7
A. Barenco et al., "Elementary gates for quantum computation," Physical Review A, Vol. 52, pp. 3457--3467, 1995.
 
8
A. Slomson, "An Introduction to Combinatorics," CRC Press, 1991.
 
9
D. Maslov, and D. M. Miller, "Comparison of the Cost Metrics for Reversible and Quantum Logic Synthesis," arXiv:quant-ph/0511008 v3, 2006.
 
10
 
11
P. Gupta, A. Agrawal, N. K Jha, "An Algorithm for Synthesis of Reversible Logic Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 11, pp. 2317--2330, 2006.
 
12
D. Maslov, G. W. Dueck, D. M. Miller, C. Negrevergne, "Quantum Circuit Simplification and Level Compaction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, in press, 2008.
13
14
Collaborative Colleagues:
Zahra Sasanian: colleagues
Mehdi Saeedi: colleagues
Mehdi Sedighi: colleagues
Morteza Saheb Zamani: colleagues