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Dynamic test compaction for a random test generation procedure with input cube avoidance
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Source
Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Scan test generation table of contents
Pages 672-677  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Irith Pomeranz  Purdue University, W. Lafayette, IN
Sudhakar M. Reddy  University of Iowa, Iowa City, IA
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 21,   Citation Count: 0
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ABSTRACT

A recent approach to test generation avoids the assignment of certain input values in order not to prevent target faults from being detected. The test generation process based on this approach is efficient; however, it generates large test sets. We develop a dynamic test compaction procedure for this approach. Our goal is to reduce the test set size by increasing the number of faults detected by each test vector, while keeping the computational complexity as low as that of the original procedure. This is achieved by avoiding the assignment of certain input values in order not to prevent subsets of faults from being detected.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Goel and B. C. Rosales, "Test Generation and Dynamic Compaction of Tests", in Proc. Test Conf., 1979 pp. 189--192.
 
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J.-S. Chang and C.-S. Lin, "Test Set Compaction for Combinational Circuits", in Proc. Asian Test Symp., 1992, pp. 20--25.
 
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Y. Matsunaga, "MINT -An Exact Algorithm for Finding Minimum Test Sets", IEICE Trans. Fundamentals., vol. E76-A, No. 10, Oct. 1993, pp. 1652--1658.
 
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S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, Dec. 1995, pp. 1496--1504.
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V. D. Agrawal, K. T. Cheng and P. Agrawal, "A Directed Search Method for Test Generation Using Concurrent Simulator," IEEE Trans. on Computer-Aided Design, Feb. 1989, pp. 131--138.
 
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I. Pomeranz and S. M. Reddy, "Forward-Looking Fault Simulation for Improved Static Compaction", IEEE Trans. on Computer-Aided Design, Oct. 2001, pp. 1262--1265.
Collaborative Colleagues:
Irith Pomeranz: colleagues
Sudhakar M. Reddy: colleagues