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Automatic formal verification of clock domain crossing signals
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Source
Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Sequential design verification table of contents
Pages 654-659  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Bing Li  Mentor Graphics Corp., San Jose, CA
Chris Ka-Kei Kwok  Mentor Graphics Corp., San Jose, CA
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 15,   Downloads (12 Months): 59,   Citation Count: 0
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ABSTRACT

In this paper, we present an approach that uses formal methods to verify Clock Domain Crossing (CDC) issues in a fully automatic way. First, we discuss various CDC schemes and the corresponding checks that need to be formally verified. Then we demonstrate how to synthesize them into assertion logic. After that a fully automatic, on-the-fly formal CDC approach is proposed. To the best of our knowledge, this is the first paper discussing fully automatic, on-the-fly formal verification of CDC signals. Experiment results show that our automatic formal CDC, when compared with the conventional post-CDC formal CDC, takes much less time, but still prove significant number of CDC checks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T. Ly, C. K. Kwok, C. Widdoes., "A methodology for verifying sequential reconvergence of clock-domain crossing signals", Design and Verification Conference, 2005.
 
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C. Cummings, "Synthesis and Scripting Techniques for Designing Multi-asynchronous Clock Designs," Synopsys Users Group (SNUG), 2001.
 
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"Clock domain crossing-closing the loop on clock domain function implementation problems", 2004. Cadence Design Systems.
 
7
N. Hand, "The need for an automated clock domain crossing verification solution", Mentor Graphics Corporation, 2006.
 
8
S. Sarwary, S. Verma, "Critical clock-domain-crossing bugs", Electronics Design, Strategy, News, Apr. 3, 2008
 
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T. Kapschitz, R. Ginosar, "Formal Verification of Synchronizers", Conference of Correct Hardware Design and Verification Methods, 2005.
 
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C. Kwok, V. Gupta, T. Ly, "Using Assertion-based verification to verify clock domain crossing signals", Design and Verification Conference, 2003.
 
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T. Kapschtiz, R. Ginosar, R. Newton, "Verifying Synchronization in Multi-Clock domain SoC", Design and Verification Conference, 2004.
 
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"CheckWare Data Book--Assertion Library", Mentor Graphics Corporation.
Collaborative Colleagues:
Bing Li: colleagues
Chris Ka-Kei Kwok: colleagues