Thermal-aware post compilation for VLIW architectures

ABSTRACT

Development of a thermal management method to reduce hotspots and to balance the temperature distribution has become an important issue. In this paper, we propose a static thermal management technique at compiler level. The target machine is a VLIW architecture where the compiler is required to schedule instructions to achieve instruction level parallelism (ILP). Two technique are proposed. The first one is register binding to balance the temperature of the register file by taking both spatial and temporal thermal information into consideration. The second one is forwarding methods including forwarding-aware architecture and instruction scheduling to reduce the access count of register file. The experimental results show that by combining the two techniques, the peak temperature reduction can reach 7.89 (°C) in the best case and 7.22 (°C) in average with only 0.9% performance penalty in average.

REFERENCES

• 1: David Brooks , Margaret Martonosi, Dynamic Thermal Management for High-Performance Microprocessors, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.171, January 20-24, 2001
• 2: Kevin Skadron , Tarek Abdelzaher , Mircea R. Stan, Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.17, February 02-06, 2002
• 3: Yingmin Li , David Brooks , Zhigang Hu , Kevin Skadron, Performance, Energy, and Thermal Considerations for SMT and CMP Architectures, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.71-82, February 12-16, 2005 [doi>10.1109/HPCA.2005.25]
• 4: K. Sankaranarayanan, S. Velusamy, M. R. Stan, and K. Skadron, "A Case for Thermal-Aware Floorplanning at the Microarchitectural Level," The Journal of Instruction-Level Parallelism Septempter 2005.
• 5: Madhu Mutyam , Feihui Li , Vijaykrishnan Narayanan , Mahmut Kandemir , Mary Jane Irwin, Compiler-directed thermal management for VLIW functional units, Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems, June 14-16, 2006, Ottawa, Ontario, Canada
• 6: Jessica H. Tseng , Krste Asanović, Banked multiported register files for high-frequency superscalar microprocessors, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 7: Fred C. Chow , John L. Hennessy, The priority-based coloring approach to register allocation, ACM Transactions on Programming Languages and Systems (TOPLAS), v.12 n.4, p.501-536, Oct. 1990 [doi>10.1145/88616.88621]
• 8: J. H. Tseng , K. Asanovic, Energy-Efficient Register Access, Proceedings of the 13th symposium on Integrated circuits and systems design, p.377, September 18-24, 2000
• 9: Intel 64 and IA-32 architectures Software Developer's Manual, Intel Corp, "http://www.intel.com/design/processor/manuals"
• 10: William Stallings, Computer Organization and Architecture: Designing for Performance (7th Edition), Prentice-Hall, Inc., Upper Saddle River, NJ, 2005
• 11: Sanghyun Park , Aviral Shrivastava , Nikil Dutt , Alex Nicolau , Yunheung Paek , Eugene Earlie, Bypass aware instruction scheduling for register file power reduction, Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems, June 14-16, 2006, Ottawa, Ontario, Canada
• 12: Weiping Liao , Joseph M. Basile , Lei He, Leakage power modeling and reduction with data retention, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.714-719, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774677]
• 13: W. Huangy, K. Sankaranarayanany, R. J. Ribandoz, M. R. Stan and K. Skadron," An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations", Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking, June. 2007
• 14: S. Rusu, G. Singer, "The First IA-64 Microprocessor", IEEE Journal of Solid-state Circuits, November 2000