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A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
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Source
Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: System level simulation and modeling table of contents
Pages 564-569  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Farhad Mehdipour  Kyushu University, Japan
Hamid Noori  Institute of Systems, Information Technologies and Nanotechnologies, Japan
Bahman Javadi  Amirkabir University of Technology, Iran
Hiroaki Honda  Institute of Systems, Information Technologies and Nanotechnologies, Japan
Koji Inoue  Kyushu University, Japan
Kazuaki Murakami  Kyushu University, Japan
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 10,   Downloads (12 Months): 30,   Citation Count: 0
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ABSTRACT

Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO*) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Enzler, R. and Platzner, M., "Application-driven design of dynamically reconfigurable processors," http://e-collection.ethbib.ethz.ch/browse/sg/092_e.html, 2001.
 
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Kim, Y., Kiemb, M. and Choi, K., "Efficient design space exploration for domain-specific optimization of coarse-grained reconfigurable architecture," In Proc. of SoC Design Conference, pp. 12--17, 2005.
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Mibench, www.eecs.umich.edu/mibench.
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Noori, H., Mehdipour, F., Inoue, K., Murakami, K., "A reconfigurable functional unit with conditional execution for multi-exit custom instructions," IEICE Trans. ELECTRON., Vol. E91-C, No. 4, April 2008.
 
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Simplescalar, www.simplescalar.com
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Collaborative Colleagues:
Farhad Mehdipour: colleagues
Hamid Noori: colleagues
Bahman Javadi: colleagues
Hiroaki Honda: colleagues
Koji Inoue: colleagues
Kazuaki Murakami: colleagues