| Automatic instrumentation of embedded software for high level hardware/software co-simulation |
| Full text |
Pdf
(390 KB)
|
Source
|
Asia and South Pacific Design Automation Conference
archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
table of contents
Yokohama, Japan
SESSION: System level simulation and modeling
table of contents
Pages 546-551
Year of Publication: 2009
ISBN:978-1-4244-2748-2
|
|
Authors
|
|
Aimen Bouchhima
|
TIMA Laboratory, CNRS/Grenoble INP/UJF, Grenoble, France
|
|
Patrice Gerin
|
TIMA Laboratory, CNRS/Grenoble INP/UJF, Grenoble, France
|
|
Frédéric Pétrot
|
TIMA Laboratory, CNRS/Grenoble INP/UJF, Grenoble, France
|
|
| Sponsors |
|
| Publisher |
IEEE Press
Piscataway, NJ, USA
|
| Bibliometrics |
Downloads (6 Weeks): 18, Downloads (12 Months): 63, Citation Count: 0
|
|
|
ABSTRACT
We propose an automatic instrumentation method for embedded software annotation to enable performance modeling in high level hardware/software co-simulation environments. The proposed "cross-annotation" technique consists of extending a retargetable compiler infrastructure to allow the automatic instrumentation of embedded software at the basic block level. Thus, target and annotated native binaries are guaranteed to have isomorphic control flow graphs (CFG). The proposed method takes into account the processor-specific optimizations at the compiler level and proves to be accurate with low simulation overhead.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
Lukai Cai , Andreas Gerstlauer , Daniel Gajski, Retargetable profiling for rapid, early system-level design space exploration, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996651]
|
| |
2
|
M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop, p.3-14, December 02-02, 2001
[doi> 10.1109/WWC.2001.15]
|
| |
3
|
|
| |
4
|
|
 |
5
|
|
| |
6
|
|
| |
7
|
J. Madsen, K. Virk, and M. J. Gonzalez. Abstract RTOS modelling for multiprocessor system-on-chip. In International Symposium on System-on-Chip. IEEE, 2003.
|
| |
8
|
|
 |
9
|
Joshua J. Pieper , Alain Mellan , JoAnn M. Paul , Donald E. Thomas , Faraydon Karim, High level cache simulation for heterogeneous multiprocessors, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996652]
|
| |
10
|
H. Posadas , F. Herrera , P. Sánchez , E. Villar , F. Blasco, System-Level Performance Analysis in SystemC, Proceedings of the conference on Design, automation and test in Europe, p.10378, February 16-20, 2004
|
 |
11
|
|
| |
12
|
|
 |
13
|
|
|