CAD challenges for 3D ICs

ABSTRACT

A fundamental shift in the technology has occurred at 90nm CMOS and beyond where the interconnect resistance has been increasing so much that the distance a clock cycle can reach has been dwindling as a fraction of the dimension of the chip. to cause a repeater explosion problem. This problem translates into an explosion of repeaters which not only added significant overhead in area but also power, as repeaters are major contributors to leakage. By reaching out to the vertical dimension, 3D technology has the potential of easing repeater explosion (Figure 1), reducing latency between units, increasing memory bandwidth and integrating heterogeneous tecnologies. However, in order to exploit the full potential of 3D technology, new challenges in the area of system level design and analysis, physical design, thermal analysis need to be addressed.

To justify the cost and complexity overhead of 3D technology, it is essential to understand and study the benefit of 3D. It is clear that the biggest performance lever of 3D is at the architecture level. There is a strong need for a architectural exploration tool that combines performance and power analysis, and thermal mapping with 3D physical floorplanning to optimize system implementation in 3D technology. This requires strong linkage between architecture level analysis tools and 3D physical planning tools. Most of the advantages of 3D will be realized with novel system architectures and physical implementations. Therefore, the tools to aid 3D implementation must also operate at the higher level.

3D interconnects have the potential of reducing critical paths delays significantly, which are typically between memory and the interfacing logic. To leverage that, current physical design infrastructure that supports 2D designs must enable 3D designs. Therefore, tools such as Physical design layout (placement, routing), timing, extraction, LVS, DRC all must support silicon layers in the third dimension. New tools that consider thermally aware physical design implementations, most importantly at the architecture and SoC level are crucial to the success of 3D as thermal issues are exacerbated in 3D implementations.

Most of the studies reporting huge benefits from 3D for wire length do not adequately consider the physical impact of vertical vias. It is crucial to consider the impact of vertical vias on the physical design of ICs, from area, latency, and thermal impact point of view. Figure 2 shows that the sweet spot of partitioning for 3D implementation lies at the unit level (where a unit is a large logical entity such as floating point logic or Instruction decode logic etc). and beyond, when considering the via impact. Therefore the 3D place and route algorithms that have been proposed in the literature will be of limited use (at least in the immediate future), since initial 3D layer partitioning will be very coarse grained and current 2D designs do a fairly good job of optimizing the critical path distance.