ACM Home Page
Please provide us with feedback. Feedback
Noise minimization during power-up stage for a multi-domain power network
Full text PdfPdf (126 KB)
Source
Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Signal/power integrity and simulation table of contents
Pages 391-396  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Wanping Zhang  Qualcomm Inc., San Diego, CA and UC San Diego, La Jolla, CA
Yi Zhu  UC San Diego, La Jolla, CA
Wenjian Yu  Tsinghua University, Beijing, China
Amirali Shayan  UC San Diego, La Jolla, CA
Renshen Wang  UC San Diego, La Jolla, CA
Zhi Zhu  Qualcomm Inc., San Diego, CA
Chung-Kuan Cheng  UC San Diego, La Jolla, CA
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 30,   Citation Count: 0
Additional Information:

abstract   references   collaborative colleagues  

Tools and Actions: Review this Article  

ABSTRACT

With the popularity of Multiple Power Domain (MPD) design, the multi-domain power network noise analysis and minimization is becoming important. This paper describes an efficient heuristic algorithm to arrange the power-up sequence in a multi-domain power network in order to minimize the noise. We present a formulation of this problem and show it is NP-complete. Therefore, we propose a simulated annealing (SA) based algorithm with preprocessing. Experimental results show that the proposed algorithm can minimize the noise close to the minimal values. In terms of efficiency, the SA algorithm is more than hundreds of times faster than the enumerating method and the running time scales well for these cases with the number of domains. In addition, we discuss the trade off between power-up efficiency and noise.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Y. Ogasahara, T. Enami, M. Hashimoto, et al., "Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 10, pp. 868--872, Oct. 2007.
 
2
 
3
 
4
5
 
6
M. Keating, D. Flynn, R. Aitken, A. Gibbons, K. Shi, Low Power Methodology Manual, Springer, 2007.
 
7
J. Salmon, N. Dour, "Circuit for independent power-up sequence of a multi-voltage chip," US Patent 6236250, 2001.
 
8
N. Ranjan, "Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer," US Patent 5862390, 1999.
 
9
Y. Kanno, et al., "Hierarchical power distribution with 20 power domains in 90nm low-power multi-CPU processor," in Proc. ISSCC, Feb. 2006, pp. 2200--2209.
 
10
T. Hattori, et al., "A power management scheme controlling 20 power domains for a single-chip mobile processor," in Proc. ISSCC, Feb. 2006, pp. 2210--2219.
 
11
Collaborative Colleagues:
Wanping Zhang: colleagues
Yi Zhu: colleagues
Wenjian Yu: colleagues
Amirali Shayan: colleagues
Renshen Wang: colleagues
Zhi Zhu: colleagues
Chung-Kuan Cheng: colleagues