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Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method
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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Advances in timing analysis and modeling table of contents
Pages 272-277  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Duo Li  University of California, Riverside, CA
Sheldon X.-D. Tan  University of California, Riverside, CA
Gengsheng Chen  Fudan Univeristy, Shanghai, China
Xuan Zeng  Fudan Univeristy, Shanghai, China
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
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ABSTRACT

In this paper, we present a novel statistical analysis approach for large power grid network analysis under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called varETBR for variational extended truncated balanced realization, is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. varETBR calculates variational response Gramians by Monte-Carlo based numerical integration considering both system and input source variations for generating the projection subspace. varETBR is very scalable for the number of variables and is flexible for different variational distributions and ranges as demonstrated in experimental results. After the reduction, Monte-Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. Experimental results, on a number of IBM benchmark circuits [15] up to 1.6 million nodes, show that the varETBR can be 4500X faster than the Monte-Carlo method and is much more scalable than one of the recently proposed approaches.


REFERENCES

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Collaborative Colleagues:
Duo Li: colleagues
Sheldon X.-D. Tan: colleagues
Gengsheng Chen: colleagues
Xuan Zeng: colleagues