| Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction |
| Full text |
Pdf
(129 KB)
|
Source
|
Asia and South Pacific Design Automation Conference
archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
table of contents
Yokohama, Japan
SESSION: Advances in timing analysis and modeling
table of contents
Pages 266-271
Year of Publication: 2009
ISBN:978-1-4244-2748-2
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
IEEE Press
Piscataway, NJ, USA
|
| Bibliometrics |
Downloads (6 Weeks): 14, Downloads (12 Months): 42, Citation Count: 0
|
|
|
ABSTRACT
Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
J. Kao, et al., "A 175-mV Multiply-Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture," IEEE J. Solid-State Circuits, vol. 37, pp. 1545--1554, Nov. 2002.
|
| |
2
|
S. Das, et al., "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction," IEEE J. Solid-State Circuits, vol. 41, pp. 792--804, Apr. 2006.
|
| |
3
|
D. Blaauw, et al., "Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance," in Int. Solid-State Circuits Conference Dig. Tech. Papers, pp. 400--401, Feb. 2008.
|
| |
4
|
|
| |
5
|
T. Nakura, et al., "Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops," in Int. Solid-State Circuits Conference Dig. Tech. Papers, pp. 402--403, Feb. 2007.
|
| |
6
|
J. Tschanz, et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE J. Solid-State Circuits, vol. 37, pp. 1396--1402, Nov. 2002.
|
|