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Aspects of GPU for general purpose high performance computing
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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: EDA acceleration using new architectures table of contents
Pages 216-223  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Reiji Suda  The University of Tokyo
Takayuki Aoki  Tokyo Institute of Technology
Shoichi Hirasawa  The University of Electro-Communications
Akira Nukada  Tokyo Institute of Technology
Hiroki Honda  The University of Eletro-Communications
Satoshi Matsuoka  Tokyo Institute of Technology
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
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ABSTRACT

We discuss hardware and software aspects of GPGPU, specifically focusing on NVIDIA cards and CUDA, from the viewpoints of parallel computing. The major weak points of GPU against newest supercomputers are identified to be and summarized as only four points: large SIMD vector length, small memory, absence of fast L2 cache, and high register spill penalty. As software concerns, we derive optimal scheduling algorithm for latency hiding of host-device data transfer, and discuss SPMD parallelism on GPUs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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T. Aoki and S. Ogawa, "Iterative Solver using CUDA for Poisson Equation," Proceedings of 36th Visualization Symposium, vol. 28, suppl. no. 1, pp. 255--258, 2008 (in Japanese).
 
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S. Hirasawa, Y. Nakanishi, H. Watanabe, and H. Honda, "Common Description Language of SIMD Instructions for Performance Portability," Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'08), pp. 52--58, 2008.
 
4
NVIDIA, "NVIDIA CUDA Compute Unified Device Architecture Programming Guide," version 2.0, 2008.
 
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The 31st TOP500 list, http://www.top500.org/, November, 2008.
 
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NVIDIA, "The CUDA Compiler Driver NVCC," version 2.0, 2008.
 
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Collaborative Colleagues:
Reiji Suda: colleagues
Takayuki Aoki: colleagues
Shoichi Hirasawa: colleagues
Akira Nukada: colleagues
Hiroki Honda: colleagues
Satoshi Matsuoka: colleagues