Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

ABSTRACT

In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

REFERENCES

• 1: Bryan Black , Donald W. Nelson , Clair Webb , Nick Samra, 3D Processing Technology and Its Impact on iA32 Microprocessors, Proceedings of the IEEE International Conference on Computer Design, p.316-318, October 11-13, 2004
• 2: S. S. Sapatnekar, "CAD for 3D circuits: Solutions and challenges," Proc. VMIC, pp. 245--251, 2007.
• 3: Brent Goplen , Sachin Sapatnekar, Thermal via placement in 3D ICs, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA [doi>10.1145/1055137.1055171]
• 4: J. Cong , Jie Wei , Yan Zhang, A thermal-driven floorplanning algorithm for 3D ICs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.306-313, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382591]
• 5: Brent Goplen , Sachin Sapatnekar, Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.86, November 09-13, 2003 [doi>10.1109/ICCAD.2003.60]
• 6: Brent Goplen , Sachin Spatnekar, Placement of 3D ICs with thermal and interlayer via considerations, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278637]
• 7: Pingqiang Zhou , Yuchun Ma , Zhouyuan Li , Robert P. Dick , Li Shang , Hai Zhou , Xianlong Hong , Qiang Zhou, 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 8: Yong Zhan , Tianpei Zhang , Sachin S. Sapatnekar, Module assignment for pin-limited designs under the stacked-Vdd paradigm, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 9: G. Bai , S. Bobba , I. N. Hajj, Simulation and optimization of the power distribution network in VLSI circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 10: Sachin S. Sapatnekar , Haihua Su, Analysis and Optimization of Power Grids, IEEE Design & Test, v.20 n.3, p.7-15, May 2003 [doi>10.1109/MDT.2003.1198680]
• 11: L. Smith, "Decoupling capacitor calculations for CMOS circuits," Proc. EPEP, pp. 101--105, 1994.
• 12: Haihua Su , Sachin S. Sapatnekar , Sani R. Nassif, An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA [doi>10.1145/505388.505405]
• 13: J. Fu et al., "Decoupling capacitor allocation for power delivery network noise reduction based on standard cell layouts," Proc. ASIC, pp. 101--104, 2003.
• 14: Jingjing Fu , Zuying Luo , Xianlong Hong , Yici Cai , Sheldon X.-D. Tan , Zhu Pan, VLSI on-chip power/ground network optimization considering decap leakage currents, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1121005]
• 15: Howard H. Chen , David D. Ling, Power supply noise analysis methodology for deep-submicron VLSI chip design, Proceedings of the 34th annual conference on Design automation, p.638-643, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266307]
• 16: Shiyou Zhao , Kaushik Roy , Cheng-Kok Koh, Decoupling capacitance allocation for power supply noise suppression, Proceedings of the 2001 international symposium on Physical design, p.66-71, April 01-04, 2001, Sonoma, California, United States [doi>10.1145/369691.369737]
• 17: Jacob R. Minz , Sung Kyu Lim , Cheng-Kok Koh, 3D module placement for congestion and power noise reduction, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA [doi>10.1145/1057661.1057770]
• 18: Eric Wong , Jacob Minz , Sung Kyu Lim, Decoupling capacitor planning and sizing for noise and leakage reduction, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233580]
• 19: G. Huang et al., "Power delivery for 3D chip stacks: Physical modeling and design implication," Proc. EPEP, pp. 205--208, 2007.
• 20: H. Hu et al., "High performance ALD HfO₂-Al₂O₃ laminate MIM capacitors for RF and mixed signal IC applications," Proc. IEDM, pp. 15.6.1--15.6.4, 2003.
• 21: Y. Tu et al., "Characterization and comparison of high-k metal-insulator-metal (MiM) capacitors in 0.13μm Cu BEOL for mixed-mode and RF applications," VLSI Symp., pp. 79--80, 2003.
• 22: P. Zurcher et al., "Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies," Proc. IEDM, pp. 153--156, 2000.
• 23: M. Armacost et al., "A high reliability metal insulator metal capacitor for 0.18μm copper technology," Proc. IEDM, pp. 157--160, 2000.
• 24: D. Roberts et al., "Application of on-chip MIM decoupling capacitor for 90nm SOI microprocessor," Proc. IEDM, pp. 72--75, 2005.
• 25: H. Sanchez et al., "Increasing microprocessor speed by massive application of on-die high-k MIM decoupling capacitors," Proc. ISSCC, pp. 2190--2199, 2006.
• 26: C.-W. Ho, A. Ruehli, and P. Brennan, "The modified nodal approach to network analysis," IEEE Trans. on Circuits Syst., vol. 22, no. 6, pp. 504--509, 1975.
• 27: J. Lou et al., "Estimating routing congestion using probabilistic analysis," IEEE Trans. on Comput.-Aided Des., vol. 21, no. 1, pp. 32--41, 2002.
• 28: "IBM-PLACE Benchmarks (version 1.0)," Available at http://er.cs.ucla.edu/benchmarks/ibm-place/.
• 29: "Predictive Technology Model," Device Group at Arizona State University, Available at http://www.eas.asu.edu/~ptm.