Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

ABSTRACT

In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or power in a closed form in terms of the variational parameters, such as the channel length, the gate oxide thickness, etc. It can accommodate various spatial correlations. The new method employs the orthogonal polynomials to represent the variational gate leakages in a closed form first, which is generated by a fast multi-dimensional Gaussian quadrature method. The total leakage currents then are computed by simply summing up the resulting orthogonal polynomials (their coefficients). Unlike many existing approaches, no grid-based partitioning and approximation are required. Instead, the spatial correlations are naturally handled by orthogonal decompositions. The proposed method is very efficient and it becomes linear in the presence of strong spatial correlations. Experimental results show that the proposed method is about 10x faster than the recently proposed method [4] with constant better accuracy.

REFERENCES

• 1: "MCNC benchmark circuit placements," http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Placement/.
• 2: A. H. ane J. Karhunen and E. Oja, Independent Component Analysis. Wiley, 2001.
• 3: Shekhar Borkar , Tanay Karnik , Vivek De, Design and reliability challenges in nanometer technologies, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996588]
• 4: Hongliang Chang , Sachin S. Sapatnekar, Full-chip analysis of leakage power under process variations, including spatial correlations, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065716]
• 5: Vivek De , Shekhar Borkar, Technology and design challenges for low power and high performance, Proceedings of the 1999 international symposium on Low power electronics and design, p.163-168, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313908]
• 6: S. G. Duvall, "Statistical circuit modeling and optimization," in Intl. Workshop Statistical Metrology, Jun 2000, pp. 56--63.
• 7: Paul Friedberg , Yu Cao , Jason Cain , Ruth Wang , Jan Rabaey , Costas Spanos, Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization, Proceedings of the 6th International Symposium on Quality of Electronic Design, p.516-521, March 21-23, 2005 [doi>10.1109/ISQED.2005.82]
• 8: R. Ghanem, "The nonlinear Gaussian spectrum of log-normal stochastic processes and variables," Journal of Applied Mechanics, vol. 66, pp. 964--973, December 1999.
• 9: Roger G. Ghanem , Pol D. Spanos, Stochastic finite elements: a spectral approach, Springer-Verlag New York, Inc., New York, NY, 1991
• 10: Khaled R. Heloue , Navid Azizi , Farid N. Najm, Modeling and estimation of full-chip leakage current considering within-die correlation, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278504]
• 11: Arieh Iserles, A first course in the numerical analysis of differential equations, Cambridge University Press, New York, NY, 1996
• 12: "Semiconductor industry association. international technology roadmap for semiconductors," 2006, http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm.
• 13: Saibal Mukhopadhyay , Kaushik Roy, Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871549]
• 14: S. Narendra, V. De, S. Borkar, D. A. Antoniadis, and A. P. Chandrakasan, "Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 2, 2004.
• 15: S. Nassif, "Delay variability: sources, impact and trends," in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb 2000, pp. 368--369.
• 16: E. Novak and K. Ritter, "Simple cubature formulas with high polynomial exactness," Constructive Approximation, vol. 15, no. 4, pp. 449--522, Dec 1999.
• 17: M. Orshansky, L. Milor, and C. Hu, "Characterization of spatial intrafield gate cd variability, its impact on circuit performance, and spatial mask-level correction," in IEEE Trans. on Semiconductor Devices, vol. 17, Feb 2004, pp. 2--11.
• 18: William H. Press , Saul A. Teukolsky , William T. Vetterling , Brian P. Flannery, Numerical recipes in C (2nd ed.): the art of scientific computing, Cambridge University Press, New York, NY, 1992
• 19: "Predictive technology model," http://www.eas.asu.edu/ptm/.
• 20: Rajeev Rao , Ashish Srivastava , David Blaauw , Dennis Sylvester, Statistical analysis of subthreshold leakage current for VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.131-139, February 2004 [doi>10.1109/TVLSI.2003.821549]
• 21: Ashish Srivastava , Robert Bai , David Blaauw , Dennis Sylvester, Modeling and analysis of leakage power considering within-die process variations, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566426]
• 22: R. Teodorescu, B. Greskamp, J. Nakano, S. R. Sarangi, A. Tiwari, and J. Torrellas, "A model of parameter variation and resulting timing errors for microarchitects," in Workshop on Architectural Support for Gigascale Integration (ASGI), Jun 2007.
• 23: S. Vrudhula, J. M. Wang, and P. Ghanta, "Hermite polynomial based interconnect analysis in the presence of process variations," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, 2006.
• 24: J. Wang , P. Ghanta , S. Vrudhula, Stochastic analysis of interconnect performance in the presence of process variations, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.880-886, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382698]
• 25: J. Xiong, V. Zolotov, and L. He, "Robust extraction of spatial correlation," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, 2007.
• 26: Dongbin Xiu , George Em Karniadakis, Modeling uncertainty in flow simulations via generalized polynomial chaos, Journal of Computational Physics, v.187 n.1, p.137-167, May 2003 [doi>10.1016/S0021-9991(03)00092-5]
• 27: Dongbin Xiu , George Em Karniadakis, The Wiener--Askey Polynomial Chaos for Stochastic Differential Equations, SIAM Journal on Scientific Computing, v.24 n.2, p.619-644, 2002 [doi>10.1137/S1064827501387826]