A low-power FPGA based on autonomous fine-grain power-gating

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A low-power FPGA based on autonomous fine-grain power-gating

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: University LSI design contest table of contents

Pages: 119-120

Year of Publication: 2009

ISBN:978-1-4244-2748-2

Authors

Shota Ishihara	Tohoku University, Sendai, Miyagi, Japan
Masanori Hariyama	Tohoku University, Sendai, Miyagi, Japan
Michitaka Kameyama	Tohoku University, Sendai, Miyagi, Japan

Sponsors

: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology

Publisher

IEEE Press Piscataway, NJ, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 74, Citation Count: 0

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abstract references collaborative colleagues

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ABSTRACT

This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell efficiently, asynchronous architecture is full exploited. The proposed FPGA is fabricated in a 90nm CMOS process with dual threshold voltages. It is more efficient in power than the synchronous FPGA at less than 30% utilization.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Yan Zhang , Jussi Roivainen , Aarne Mammela, Clock-Gating in FPGAs: A Novel and Comparative Evaluation, Proceedings of the 9th EUROMICRO Conference on Digital System Design, p.584-590, August 30-September 01, 2006 [doi>10.1109/DSD.2006.32]
	2	Arifur Rahman, Satyaki Das and Tim Tuan and Steve Trim-berger, "Determination of Power Gating Granularity for FPGA Fabric," CICC, pp. 9--12, 2006.
	3	Masanori Hariyama, Shota Ishihara, Chang Chia Wei and Michitaka Kameyama, "A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture," A-SSCC, pp. 380--383, 2007.

Collaborative Colleagues:

Shota Ishihara: colleagues

Masanori Hariyama: colleagues

Michitaka Kameyama: colleagues

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