| A 300 nW, 7 ppm/°C CMOS voltage reference circuit based on subthreshold MOSFETs |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
table of contents
Yokohama, Japan
SESSION: University LSI design contest
table of contents
Pages 95-96
Year of Publication: 2009
ISBN:978-1-4244-2748-2
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IEEE Press
Piscataway, NJ, USA
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Downloads (6 Weeks): 8, Downloads (12 Months): 37, Citation Count: 0
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 ABSTRACT
An ultra-low power CMOS voltage reference circuit has been fabricated in a 0.35-μm standard CMOS process. The circuit generates a reference voltage based on threshold voltage of a MOSFET at absolute zero temperature. Theoretical analyses and experimental results showed that the circuit generates a quite stable reference voltage of 745 mV on average. The temperature coefficient and line sensitivity of the circuit were 7 ppm/°C and 20 ppm/V, respectively. The power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The circuit consists of subthreshold MOSFETs with a low-power dissipation of 0.3 μW or less and a 1.5-V power supply. Because the circuit generates a reference voltage based on threshold voltage of a MOSFET in an LSI chip, it can be used as an on-chip process monitoring circuit and as a part of the on-chip process compensation circuit systems.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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