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Thermal optimization in multi-granularity multi-core floorplanning
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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2009 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Dealing with thermal issues table of contents
Pages 43-48  
Year of Publication: 2009
ISBN:978-1-4244-2748-2
Authors
Michael B. Healy  School of Electrical and Computer Engineering
Hsien-Hsin S. Lee  School of Electrical and Computer Engineering
Gabriel H. Loh  Georgia Institute of Technology
Sung Kyu Lim  School of Electrical and Computer Engineering
Sponsors
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS : Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society
IPSJ SIGSLDM : Information Processing Society of Japan - SIG System LSI Design Methodology
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 18,   Downloads (12 Months): 79,   Citation Count: 0
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ABSTRACT

Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the consideration of all of these factors at an early stage. Toward this goal, this work presents the first adaptive multi-granularity multi-core microarchitecture-level floorplanner that simultaneously optimizes temperature and performance, and considers memory bus length. We include simultaneous optimization at both the module-level and the core/cache-bank level. Related experiments show that our methodology is effective for optimizing multi-core architectures.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
Michael B. Healy: colleagues
Hsien-Hsin S. Lee: colleagues
Gabriel H. Loh: colleagues
Sung Kyu Lim: colleagues