| Analysis of communication delay bounds for network on chips |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Yokohama, Japan
SESSION: On-chip communication architectures
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Pages: 7-12
Year of Publication: 2009
ISBN:978-1-4244-2748-2
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Authors
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Yue Qian
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National University of Defense Technology, China
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Zhonghai Lu
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Royal Institute of Technology, Sweden
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Wenhua Dou
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National University of Defense Technology, China
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IEEE Press
Piscataway, NJ, USA
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| Bibliometrics |
Downloads (6 Weeks): 12, Downloads (12 Months): 78, Citation Count: 1
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ABSTRACT
In network-on-chip, computing worst-case delay bound for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource contention scenarios. In this paper, we present an analysis technique to derive the communication delay bound for individual flows. Based on a network contention model, this technique, which is topology independent, employs the network calculus theory to first compute the equivalent service curve for individual flows and then calculate their packet delay bound. To exemplify our method, we also present the derivation of a closed-form formula to calculate the delay bound for all-to-one gather communication. Our experimental results demonstrate the theoretical bounds are correct and tight.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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