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Silicon feedback to improve frequency of high-performance microprocessors: an overview
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International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents
San Jose, California
TUTORIAL SESSION: Embedded tutorial: Learning from silicon: correlating measurements, models and design table of contents
Pages 778-782  
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
Authors
Chandramouli Kashyap  Intel Corporation, Hillsboro, OR
Pouria Bastani  University of California - Santa Barbara
Kip Killpack  Intel Corporation, Hillsboro, OR
Chirayu Amin  Intel Corporation, Hillsboro, OR
Sponsors
: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 10,   Downloads (12 Months): 28,   Citation Count: 0
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ABSTRACT

In modern high-performance microprocessors designed using advanced process technologies, the frequency of the part is often slower than what the static timing analysis tools predict before tape out. We give an overview of techniques used to observe the failing path on the tester, identify the dominant devices impacting the delay of the path, and learn from the failing path to fix other similar paths in the design. In particular, we describe a Support Vector Machine based approach for learning from speedpaths observed in silicon.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Bastani, B. Lee, L. Wang, M. Abadir, "Analyzing the risk of timing modeling based on path delay test," Proc. ITC, 2007.
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B. Gottlieb, et al, "Silicon Debug: What Do You Do When Your ASIC Does Not Work as Fast as Expected?" Proc. DAC, 2004.
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D. Barton, P. Tangyunyong, J. Soden, A. Liang, F. Low, et al, "Infrared Light Emission From Semiconductor Devices," ISTFA Proc. 1996.
 
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P. Larsson and C. Svensson, "Noise in digital dynamic CMOS circuits," IEEE J. Solid-State Circuits June 1994, pp. 655--663.
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Collaborative Colleagues:
Chandramouli Kashyap: colleagues
Pouria Bastani: colleagues
Kip Killpack: colleagues
Chirayu Amin: colleagues