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ABSTRACT

Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defecttolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130nm technology, with minimal impact of VLSI design and test flows.

REFERENCES

• 1: William J. Dally , Brian Towles, Route packets, not wires: on-chip inteconnection networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 2: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 3: R. S. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," Proceedings of the IEEE, vol. 94, no. 6, June 2006.
• 4: A. W. Topol , D. C. La Tulipe, Jr. , L. Shi , D. J. Frank , K. Bernstein , S. E. Steen , A. Kumar , G. U. Singco , A. M. Young , K. W. Guarini , M. Ieong, Three-dimensional integrated circuits, IBM Journal of Research and Development, v.50 n.4/5, p.491-506, July 2006
• 5: N. Miyakawa, T. Maebashi, N. Nakamura, S. Nakayama, E. Hashimoto, and S. Toyoda, New Multi-Layer Stacking Technology and Trial Manufacture, November 2007, honda Research Institute Japan Co. Ltd.
• 6: B. Swinnen, W. Ruythooren, P. D. M. L. Bogaerts, L. Carbonell, K. D. Munck, B. Eyckens, S. Stoukatch, Tezcan, D. Sabuncuoglu, Z. Tokei, J. Vaes, J. V. Aelst, and E. Beyne, "3d integration by cu-cu thermocompression bonding of extremely thinned bulk-si die containing 10 um pitch through-si vias," pp. 1--4, 2006.
• 7: A. W. T. et all, "Enabling soi based assembly technology for three dimensional integrated circuits," pp. 352--355, IEDM 2005.
• 8: Jongman Kim , Chrysostomos Nicopoulos , Dongkook Park , Reetuparna Das , Yuan Xie , Vijaykrishnan Narayanan , Mazin S. Yousif , Chita R. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures, Proceedings of the 34th annual international symposium on Computer architecture, June 09-13, 2007, San Diego, California, USA
• 9: S. Fujita, K. Nomura, K. Abe, and T. Lee, "3d on-chip networking technology based on post-silicon devices for future networks-on-chip," in Nano-Networks and Workshops, September 2006, pp. 1--5.
• 10: S. Fujita, K. Nomura, K. Abe, and T. H. Lee, "3-d nanoarchitectures with carbon nanotube mechanical switches for future on-chip network beyond cmos architecture," IEEE Transactions on Circuits and Systems Part I: Regular Papers, vol. 54, no. 11, pp. 2472--2479, November 2007.
• 11: M. Rencher and F. Schellenberg, "Why interconnect and litography modeling impacts yield," in What's Yield got to do with IC.
• 12: Igor Loi , Federico Angiolini , Luca Benini, Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
• 13: Igor Loi , Federico Angiolini , Luca Benini, Developing mesochronous synchronizers to enable 3D NoCs, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany [doi>10.1145/1403375.1403717]
• 14: S. Spiesshoefer and et al, "Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development," in Electronic Components and Technology Conference, 2004.
• 15: R. Patti, "Impact of wafer-level 3d stacking on the yield of ics," in Future Fab Intl, September 2007. {Online}. Available: http://www.future-fab.com/documents.asp?d_id=4415
• 16: N. Miura, D. Mizoguchi, M. Inoue, T. Sakurai, and T. Kuroda, "A 195-gb/s 1.2-w inductive inter-chip wireless superconnect with transmit power control scheme for 3-d-stacked system in a package," IEEE journal of solid state circuits, vol. 41, no. 1, pp. 23--34, january 2006.
• 17: Kuan-Neng Chen , Andy Fan , Rafael Reif, Microstructure examination of copper wafer bonding, Journal of Electronic Materials, v.30 n.4, p.331-335, April 2001 [doi>10.1007/s11664-001-0039-6]
• 18: K.-N. Chen, C. Tan, A. Fan, and R. Reif, "Morphology and bond strength of copper wafer bonding," in Electrochem. Solid-State Lett., vol. 7, 2004, pp. 14--16.
• 19: A. Papanikolaou, M. Miranda, H. Wang, F. Catthoor, M. Satyakiran, P. Marchal, B. Kaczer, C. Bruynseraede, and Z. Tokei, "Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design," pp. 342--347, IEDM 2006.
• 20: K. N. Chen, A. Fan, and R. Reif, "Interfacial morphologies and possible mechanisms of copper wafer bonding," in http://www-mtl.mit.edu/users/reif/papers/2002-knchen-JMS-manuscript.pdf.
• 21: F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini, "A layoutaware analysis of networks-on-chip and traditional interconnects for mpsocs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 421--434, March 2007.