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Advancing supercomputer performance through interconnection topology synthesis
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International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents
San Jose, California
SESSION: System-level optimization issues in highly parallel architectures table of contents
Pages 555-558  
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
Authors
Yi Zhu  University of California, San Diego, La Jolla, CA
Michael Taylor  University of California, San Diego, La Jolla, CA
Scott B. Baden  University of California, San Diego, La Jolla, CA
Chung-Kuan Cheng  University of California, San Diego, La Jolla, CA
Sponsors
: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 39,   Citation Count: 0
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ABSTRACT

In today's many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow to discover the best topology in terms of the communication latency and physical constraints. First a set of representative candidate topologies are generated for the interconnection networks among computing chips; then an efficient multi-commodity flow algorithm is devised to evaluate the performance. The experiments show that the best topologies identified by our algorithm can achieve better average latency compared to the existing networks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Yi Zhu: colleagues
Michael Taylor: colleagues
Scott B. Baden: colleagues
Chung-Kuan Cheng: colleagues