Take a look at the new version of this page: [ beta version ]. Tell us what you think.

ABSTRACT

Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed postfabrication tuning knob called voltage interpolation. The paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. The paper explores the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks and shows that the scheme can be used to mitigate overhead arising from random and correlated within-die process variations. The analysis shows that the scheme can match the nominal delay target with a 10% power cost, or for the same power budget, incur only a 9% delay overhead after variations.

REFERENCES

• 1: Justin Gregg , Tom W. Chen, Post silicon power/performance optimization in the presence of process variations using individual well-adaptive body biasing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.3, p.366-376, March 2007 [doi>10.1109/TVLSI.2007.893626]
• 2: J. W. Tschanz, J. T. Kao, and S. G. Narendra, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid-State Circuits, November 2002.
• 3: X. Liang, D. Brooks, and G.-Y. Wei, "A process-variation-tolerant floating-point unit with voltage interpolation and variable latency," in International Solid-State Circuits Conference, Feb. 2008.
• 4: Sun Microsystems Inc., "OpenSPARC T1 Chip Design," http://www.opensparc.net/.
• 5: Azadeh Davoodi , Ankur Srivastava, Variability driven gate sizing for binning yield optimization, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147152]
• 6: Yuanlin Lu , Vishwani D. Agrawal, Statistical Leakage and Timing Optimization for Submicron Process Variation, Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems, p.439-444, January 06-10, 2007 [doi>10.1109/VLSID.2007.148]
• 7: Yang Xu , Kan-Lin Hsiung , Xin Li , Ivan Nausieda , Stephen Boyd , Lawrence Pileggi, OPERA: optimization with ellipsoidal uncertainty for robust analog IC design, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065746]
• 8: A. Srivastava, T. Kachru, and D. Sylvester, "Low-power-design space exploration considering process variation using robust optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 67--79, 2007.
• 9: D. Sinha, N. V. Shenoy, and H. Zhou, "Statistical timing yield optimization by gate sizing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 10, pp. 1140--1146, October 2006.
• 10: Sarvesh H Kulkarni , Dennis Sylvester , David Blaauw, A statistical framework for post-silicon tuning through body bias clustering, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233511]
• 11: Murari Mani , Ashish K. Sing , Michael Orshansky, Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233507]
• 12: Radu Teodorescu , Jun Nakano , Abhishek Tiwari , Josep Torrellas, Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing, Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, p.27-42, December 01-05, 2007 [doi>10.1109/MICRO.2007.27]
• 13: Jeng-Liang Tsai , Lizheng Zhang, Statistical timing analysis driven post-silicon-tunable clock-tree synthesis, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.575-581, November 06-10, 2005, San Jose, CA
• 14: Diana Marculescu , Emil Talpes, Variability and energy awareness: a microarchitecture-level perspective, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065588]
• 15: Kimiyoshi Usami , Mark Horowitz, Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design, p.3-8, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224083]
• 16: Kanak Agarwal , Kevin Nowka, Dynamic Power Management by Combination of Dual Static Supply Voltages, Proceedings of the 8th International Symposium on Quality Electronic Design, p.85-92, March 26-28, 2007 [doi>10.1109/ISQED.2007.66]
• 17: Faraday Technology Corporation, "UMC 0.13um Logic core cell library," http://www.faraday-tech.com/.
• 18: A. Agarwal, V. Zolotov, and D. Blaauw, "Statistical timing analysis using bounds and selective enumeration," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 9, September 2003.