| Layout decomposition for double patterning lithography |
| Full text |
Pdf
(937 KB)
|
Source
|
International Conference on Computer Aided Design
archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
table of contents
San Jose, California
SESSION: DFM methods for advanced lithography
table of contents
Pages 465-472
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
|
|
Authors
|
|
Andrew B. Kahng
|
UC San Diego, La Jolla, CA and Blaze DFM, Inc., Sunnyvale, CA
|
|
Chul-Hong Park
|
UC San Diego, La Jolla, CA
|
|
Xu Xu
|
Blaze DFM, Inc., Sunnyvale, CA
|
|
Hailong Yao
|
UC San Diego, La Jolla, CA
|
|
| Sponsors |
|
| Publisher |
IEEE Press
Piscataway, NJ, USA
|
| Bibliometrics |
Downloads (6 Weeks): 21, Downloads (12 Months): 70, Citation Count: 2
|
|
|
ABSTRACT
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. We evaluate our technique on both real-world and artificially generated testcases in 45nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Calibre User's Manual. http://www.mentor.com/.
|
| |
2
|
Design Compiler User's Manual. http://www.synopsys.com/.
|
| |
3
|
SOC Encounter User's Manual. http://www.cadence.com/.
|
| |
4
|
International Technology Roadmap for Semiconductors. http://public.itrs.net/.
|
| |
5
|
G. E. Bailey et al., "Double Pattern EDA Solutions for 32nm HP and Beyond", Proc. SPIE Conf. on Design for Manufacturability Through Design-Process Integration, 2007, pp. 65211K-1 - 65211K-12.
|
| |
6
|
G. Capetti et al., "Sub k1 = 0.25 Lithography with Double Patterning Technique for 45nm Technology Node Flash Memory Devices at 193nm", Proc. SPIE Conf. on Optical Microlithography, 2007, pp. 65202K-1 - 65202K-12.
|
| |
7
|
C. Chiang , A. Kahng , S. Sinha , X. Xu , A. Zelikovsky, Bright-Field AAPSM Conflict Detection and Correction, Proceedings of the conference on Design, Automation and Test in Europe, p.908-913, March 07-11, 2005
[doi> 10.1109/DATE.2005.84]
|
| |
8
|
C. Chiang , A. B. Kahng , S. Sinha , X. Xu, Fast and efficient phase conflict detection and correction in standard-cell layouts, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.149-156, November 06-10, 2005, San Jose, CA
|
| |
9
|
M. Drapeau, V. Wiaux, E. Hendrickx, S. Verhaegen and T. Machida, "Double Patterning Design Split Implementation and Validation for the 32nm Node", Proc. SPIE Conf. on Design for Manufacturability Through Design-Process Integration, 2007, 652109-1-652109-15.
|
| |
10
|
M. Dusa et al., "Pitch Doubling Through Dual-Patterning Lithography Challenges in Integration and Litho Budgets", Proc. SPIE Conf. on Optical Microlithography, 2007, pp. 65200G-1--65200G-10.
|
| |
11
|
J. Finders, M. Dusa and S. Hsu, "Double Patterning Lithography: The Bridge Between Low k1 ArF and EUV", Microlithography World, Feb. 2008.
|
| |
12
|
|
| |
13
|
A. B. Kahng, X. Xu and A. Zelikovsky, "Fast Yield-Driven Fracture for Variable Shaped-Beam Mask Writing", Proc. SPIE Conf. on Photomask and Next-Generation Lithography Mask Technology, 2006, pp. 62832R-1--62832R-9.
|
| |
14
|
S.-M. Kim et al., "Issues and Challenges of Double Patterning Lithography in DRAM", Proc. SPIE Conf. on Optical Microlithography, 2006, pp. 65200H-1 - 65200H-7.
|
| |
15
|
C. Lim et al., "Positive and Negative Tone Double Patterning Lithography for 50nm Flash Memory", Proc. SPIE Conf. on Optical Microlithography, 2006, pp. 615410-1--615410-8.
|
| |
16
|
C. Mack, Fundamental Principles of Optical Lithography: The Science of Microfabrication, Wiley, 2007.
|
| |
17
|
M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, and M. Van Hove, "Double Patterning Scheme for Sub-0.25 k1 Single Damascene Structures at NA=0.75, λ=193nm", Proc. SPIE Conf. on Optical Microlithography, 2005, pp. 1508--1518.
|
| |
18
|
W.-Y. Jung et al., "Patterning With Spacer for Expanding the Resolution Limit of Current Lithography Tool", Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, vol. 6125 pp. 61561J-1 - 61561J-9, 2006.
|
| |
19
|
J. Rubinstein and A. R. Neureuther, "Post-Decomposition Assessment of Double Patterning Layout", Proc. SPIE Conf. on Optical Microlithography, 2008, pp. 69240O-1 - 69240O-12.
|
|