| Decoupling capacitance allocation for timing with statistical noise model and timing analysis |
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International Conference on Computer Aided Design
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Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
table of contents
San Jose, California
SESSION: Physical design for performance improvement & noise immunity
table of contents
Pages 420-425
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
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Authors
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Takashi Enami
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Osaka University, Suita, Osaka, Japan
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Masanori Hashimoto
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Osaka University, Suita, Osaka, Japan
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Takashi Sato
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Tokyo Institute of Technology, Nagatsuta, Midori-ku, Yokohama, Japan
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IEEE Press
Piscataway, NJ, USA
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Downloads (6 Weeks): 1, Downloads (12 Months): 24, Citation Count: 0
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ABSTRACT
This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a gate delay at all the switching timing within a cycle, and devised an efficient sensitivity calculation of timing to decap for decap allocation. The proposed method, which is based on a statistical noise modeling and timing analysis, accelerates the sensitivity calculation with an approximation and adjoint sensitivity analysis. Experimental results show that the decap allocation based on the sensitivity analysis efficiently optimizes the worst-case circuit delay within a given decap budget. Compared to the maximum decap placement, the delay improvement due to decap increases by 5% even while the total amount of decap is reduced to 40%.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Hang Li , Zhenyu Qi , Sheldon X.-D. Tan , Lifeng Wu , Yici Cai , Xianlong Hong, Partitioning-based approach to fast on-chip decap budgeting and minimization, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA
[doi> 10.1145/1065579.1065627]
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2
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H. Su, S. S. Sapatnekar, and S. R. Nassif, "Optimal Decoupling Capacitor Sizing and Placement for Standard-Cell Layout Designs," IEEE Trans. CAD, Vol. 22, No. 4, pp. 428--436, 2003.
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3
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4
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T. R.-Arabi, G. Taylor, M. Ma, and C. Webb, "Design & validation of the Pentium III and Pentium 4 processors power delivery," in proc. VLSI Circuits, pp. 220--223, 2002.
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5
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6
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OPENCORES.ORG, http://www.opencores.org/.
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7
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T. L. Pillage, R. A. Rohrer, and C. Visweswariah, "Electronic Circuit & System Simulation Methods," MC Graw-Hill, 1995.
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8
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C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996663]
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9
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Jinjun Xiong , Vladimir Zolotov , Natesan Venkateswaran , Chandu Visweswariah, Criticality computation in parameterized statistical timing, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
[doi> 10.1145/1146909.1146929]
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10
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Chieki Mizuta , Jiro Iwai , Ken Machida , Tetsuro Kage , Hiroo Masuda, Large-scale linear circuit simulation with an inversed inductance matrix, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, January 27-30, 2004, Yokohama, Japan
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