Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization

ABSTRACT

A new approach to the problem of clock buffer polarity assignment for minimizing power/ground noise on the clock network is presented. The previous approaches solve the assignment problem in two separate steps: (step 1) generating a clock routing tree of minimum total wirelength, satisfying the clock skew constraint and then (step 2) inserting buffering elements with their polarities under the objective of minimizing power/ground noise while satisfying the clock skew constraint. Yet, there is no easy way to predict the result of step 2 during step 1. In our approach, we place the primary importance on the cost of power/ground noise. Consequently, we try to minimize the cost of power/ground noise first and then to construct a clock routing tree later while satisfying the clock skew constraint. Through experimentation using several benchmark circuits, it is shown that this approach is quite effective and produces very good solutions, reducing the power/ground noise by 75% and the peak current by 26% at the expense of 5% wirelength overhead compared to that produced by the conventional approach.

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