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Importance sampled circuit learning ensembles for robust analog IC design
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International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents
San Jose, California
SESSION: Analog and memory design enablers table of contents
Pages 396-399  
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
Authors
Peng Gao  ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium
Trent McConaghy  ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium and Solido Design Automation Inc., Saskatoon, Canada
Georges Gielen  ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium
Sponsors
: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 11,   Downloads (12 Months): 26,   Citation Count: 0
Additional Information:

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ABSTRACT

This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore's Law, by doing boosting-style importance sampling on digital-sized circuits to achieve the target analog behavior. ISCLEs consists of: (1) a boosting algorithm developed specifically for circuit assembly; (2) an ISCLEs-specific library of possible digital-sized circuit blocks; and (3) a recently-developed multi-topology sizing technique to automatically determine each block's topology and device sizes. ISCLEs is demonstrated on design of a sinusoidal function generator and a flash A/D converter, showing promise to robustly scale with shrinking process geometries.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Peng Gao: colleagues
Trent McConaghy: colleagues
Georges Gielen: colleagues