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Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example
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International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents
San Jose, California
SESSION: Circuit and system optimization and modeling table of contents
Pages 314-321  
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
Authors
Ranko Sredojević  Massachusetts Institute of Technology, Cambridge, MA
Vladimir Stojanović  Massachusetts Institute of Technology, Cambridge, MA
Sponsors
: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 9,   Downloads (12 Months): 54,   Citation Count: 0
Additional Information:

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ABSTRACT

Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-speed links are particularly hard to analyze because of the complex interplay of device/circuit parasitics and channel filtering operation. In this paper we introduce optimization-based framework for link design-space exploration, connecting the link transmission quality and top-level filter settings with circuit power, sizing and biasing. We derive a special analytical discrete time representation that avoids the size explosion of the symbolic problem description improving the parsing and solver time by orders of magnitude and making this joint optimization possible in real-time. This robust and accurate problem formulation is derived in signomial form and is compatible with existing optimization approaches to circuit sizing. We demonstrate this optimization framework on a link design-space exploration example, investigating trade-offs between the transmit preemphasis and linear receiver equalizer and their impact on overall link power vs. data rate.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
B. Casper, M. Haycock, and R. Mooney, "An accurate and efficient analysis method for multi-gb/s chip-to-chip signaling schemes," Symposium on VLSI Circuits Digest of Technical Papers, 2002., no. SN -, pp. 54--57, 2002.
 
2
V. Stojanovic and M. Horowitz, "Modeling and analysis of high-speed links," in IEEE Custom Integrated Circuits Conference, 2003.
 
3
P. Hanumolu, B. Casper, R. Mooney, G.-Y. Wei, and U.-K. Moon, "Analysis of pll clock jitter in high-speed serial links," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 11 SN - 1057--7130, pp. 879--886, 2003.
 
4
H. Hatamkhani and C. Ken Yang, "A study of the optimal data rate for minimum power of i/os," IEEE Transactions on Circuits and Systems II, vol. 53, no. 11 SN - 1057--7130, pp. 1230--1234, 2006.
 
5
M. Hershenson, S. Boyd, and T. Lee, "Optimal design of a cmos op-amp via geometric programming," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1 SN - 0278--0070, pp. 1--21, 2001.
 
6
P. Mandal and V. Visvanathan, "Cmos op-amp sizing using a geometric programming formulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 22--38, 2001.
7
 
8
D. Colleran, C. Portmann, A. Hassibi, C. Crusius, S. Mohan, S. Boyd, T. Lee, and M. del Mar Hershenson, "Optimization of phase-locked loop circuits via geometric programming," Proceedings of the IEEE Custom Integrated Circuits Conference, 2003., no. SN -, pp. 377--380, 2003.
 
9
 
10
 
11
C. Maranas and C. Floudas, "Global optimization in generalized geometric programming," pp. 351--370, 1997.
 
12
 
13
 
14
V. Stojanovic, A. Amirkhany, and M. Horowitz, "Optimal linear precoding with theoretical and practical data rates in high-speed seriallink backplane communication," IEEE International Conference on Communications, vol. 5, no. SN -, pp. 2799--2806 Vol.5, 2004.
15
 
16
 
17
R. Farjad-Rad, N. Hiok-Taiq, M. Edward Lee, R. Senthinathan, W. Dally, A. Nguyen, R. Rathi, J. Poulton, J. Edmondson, J. Tran, and H. Yazdanmehr, "0.622-8.0 gbps 150 mw serial io macrocell with fully flexible preemphasis and equalization," Symposium on VLSI Circuits, 2003. Digest of Technical Papers. 2003, no. SN -, pp. 63--66, 2003.
 
18
J. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara, M. Horowitz, and K. Donnelly, "Equalization and clock recovery for a 2.5-10-gb/s 2-pam/4-pam backplane transceiver cell," IEEE Journal of Solid-State Circuits, vol. 38, no. 12 SN - 0018-9200, pp. 2121--2130, 2003.
Collaborative Colleagues:
Ranko Sredojević: colleagues
Vladimir Stojanović: colleagues