|
ABSTRACT
The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Rob A. Rutenbar, L. Richard Carley, John M. Cohn, and David J. Garrod. Analog Device-Level Layout Automation. Kluwer Academic Publishers, 1994.
|
| |
2
|
Alan Hastings. The Art of Analog Layout. Prentice-Hall, 2001.
|
| |
3
|
Enrico Malavasi and Alberto Sangiovanni-Vincentelli. Area routing for analog layout. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 12(8):1186--1197, August 1993.
|
| |
4
|
D. W. Jepsen and C. D. Gellat Jr. Macro placement by monte carlo annealing. In IEEE International Conference on Computer Design (ICCD), pages 495--498, 1983.
|
| |
5
|
John M. Cohn, David J. Garrod, Rob A. Rutenbar, and L. Richard Carley. Koan/anagram ii: New tools for device-level analog placement and routing. IEEE Journal of Solid-State Circuits SC, 26(3):330--342, March 1991.
|
| |
6
|
Koen Lampert, Georges Gielen, and Willy M. Sansen. A performancedriven placement tool for analog integrated circuits. IEEE Journal of Solid-State Circuits SC, 30(7):773--780, July 1995.
|
| |
7
|
Enrico Malavasi, Edoardo Charbon, Eric Felt, and Alberto Sangiovanni-Vincentelli. Automation of ic layout with analog constraints. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 15(8):923--942, August 1996.
|
 |
8
|
Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309928]
|
| |
9
|
H. Murata, K. Fujiyoshi, S. Nakatake, and Kajitani. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 15(12):1518--1524, 1996.
|
| |
10
|
Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
|
 |
11
|
Yingxin Pang , Florin Balasa , Koen Lampaert , Chung-Kuan Cheng, Block placement with symmetry constraints based on the O-tree non-slicing representation, Proceedings of the 37th conference on Design automation, p.464-467, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337545]
|
| |
12
|
Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
|
| |
13
|
|
| |
14
|
Jai-Ming Lin and Yao-Wen Chang. Tcg-s: Orthogonal coupling of p-admissible representations for general floorplans. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 23(6):968--980, June 2004.
|
 |
15
|
Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337541]
|
| |
16
|
Florin Balasa, Sarat C. Maruvada, and Karthik Krishnamoorthy. On the exploration of the solution space in analog placement with symmetry constraints. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 23(2):177--191, February 2004.
|
| |
17
|
Ammar Nassaj, Jens Lienig, and Göran Jerke. A constraint-driven methodology for placement of analog and mixed-signal integrated circuits. In IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2008.
|
| |
18
|
Florian Balasa and Koen Lampaert. Symmetry within the sequencepair representation in the context of placement for analog design. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 19(7):721--731, July 2000.
|
| |
19
|
Karthik Krishnamoorthy, Sarat C. Maruvada, and Florin Balasa. Fast evaluation of symmetric-feasible sequence-pairs for analog topological placement. In 5th IEEE Int. Conf. on ASIC (ASICON), pages 71--74, 2003.
|
| |
20
|
Karthik Krishnamoorthy, Sarat C. Maruvada, and Florin Balasa. Topological placement with multiple symmetry groups of devices for analog layout design. In IEEE International Symposium on Circuits and Systems (ISCAS), pages 2032--2035, May 2007.
|
 |
21
|
|
 |
22
|
|
| |
23
|
David A. Johns and Ken Martin. Analog Integrated Circuit Design. John Wiley & Sons, 1997.
|
| |
24
|
|
 |
25
|
|
| |
26
|
R. H. J. M. Otten. Efficient floorplan optimization. In IEEE International Conference on Computer Design (ICCD), pages 499--501, October 1983.
|
| |
27
|
|
| |
28
|
J. Fisher and R. Koch. A highly linear CMOS buffer amplifier. IEEE Journal of Solid-State Circuits SC, 22:330--334, 1987.
|
 |
29
|
|
|