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Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits
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International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents
San Jose, California
SESSION: Modeling and simulation of process variability table of contents
Pages 278-285  
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
Authors
Yiming Li  National Chiao Tung University, Hsinchu, Taiwan
Chih-Hong Hwang  National Chiao Tung University, Hsinchu, Taiwan
Ta-Ching Yeh  National Chiao Tung University, Hsinchu, Taiwan
Tien-Yeh Li  National Chiao Tung University, Hsinchu, Taiwan
Sponsors
: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
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ABSTRACT

Modeling of device variability is crucial for the accuracy of timing in circuits and systems, and the stability of high-frequency application. Unfortunately, due to the randomness of dopant position in device, the fluctuation of device gate capacitance is nonlinear and hard to be modeled in current compact models. Therefore, a large-scale statistically sound "atomistic" device/circuit coupled simulation approach is proposed to characterize the random-dopant-induced characteristic fluctuations in 16-nm-gate CMOS integrated circuits concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations. The variations of transition time of digital circuit (inverter, NAND, and NOR gates) and high-frequency characteristic of common-source amplifier are estimated. For the digital circuits, the function-dependent and circuit-topology-dependent characteristic fluctuations resulted from random nature of discrete dopants is for the first time discussed. This study provides an insight into random-dopant- induced intrinsic timing and high-frequency characteristic fluctuations. The accuracy of the simulation technique is confirmed by the use of experimentally calibrated transistor physical model.


REFERENCES

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1
D. M. Fried, J. M. Hergenrother, A. W. Topol, L. Chang, L. Sekaric, J. W. Sleight, S. McNab, J. Newbury, S. Steen, G. Gibson, Y. Zhang, N. Fuller, J. Bucchignano, C. Lavoie, C. Cabral, D. Canaperi, O. Dokumaci, D. Frank, E. Duch, I. Babich, K. Wong, J. Ott, C. Adams, T. Dalton, R. Nunes, D. Medeiros, R. Viswanathan, M. Ketchen, M. Ieong, W. Haensch, and K. W. Guarini, "Aggressively scaled (0.143 μm2) 6T-SRAM cell for the 32 nm node and beyond," in Int. Electron Devices Meeting Tech. Dig., pp. 261--264, Dec. 2004.
 
2
H. Lee, L.-E. Yu, S.-W. Ryu, J.-W. Han, K. Jeon, D.-Y. Jang, K.-H. Kim, J. Lee, J.-H. Kim, S. C. Jeon, G. S. Lee, J. S. Oh, Y. C. Park, W. H Bae, H. M. Lee, J. M. Yang, J. J. Yoo, S. I. Kim and Y.-K. Choi, "Sub-5nm All-Around Gate FinFET for Ultimate Scaling," in VLSI Technol. Tech. Symp. Dig., pp. 58--59, 2006.
 
3
F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C. Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, "5nm-gate nanowire FinFET," in VLSI Technol. Tech. Symp. Dig., pp. 196--197, June 2004.
4
5
 
6
V. Dimitrov, J. B. Heng, K. Timp, O. Dimauro, R. Chan, J. Feng, W. Hafez, T. Sorsch, W. Mansfield, J. Miner, A. Kornblit, F. Klemens, J. Bower, R. Cirelli, E. Ferry, A. Taylor, M. Feng, and G. Timp, "High Performance, sub-50nm MOSFETS for Mixed Signal Applications," in Int. Electron Devices Meeting Tech. Dig., pp. 213--216, Dec. 2005.
 
7
Q. Li, J. Zhang, Wei Li, J. S. Yuan, Yuan Chen, and Anthony S. Oates, "RF Circuit Performance Degradation Due to Soft Breakdown and Hot-Carrier Effect in Deep-Submicrometer CMOS Technology," IEEE Trans. Microwave Theory Tech., vol. 49, no. 9, pp. 1546--1551, Sept. 2001.
 
8
H.-S. Wong, Y. Taur, and D. J. Frank, "Discrete Random Dopant Distribution Effects in Nanometer-Scale MOSFETs," Microelectronics Reliability, vol. 38, no. 9, pp. 1447--1456, Sept. 1999.
 
9
Y. Li and S.-M. Yu, "Comparison of Random-Dopant-Induced Threshold Voltage Fluctuation in Nanoscale Single-, Double-, and Surrounding-Gate Field-Effect Transistors," Jpn. J. Appl. Phys., vol. 45, no. 9A, pp. 6860--6865, Sept. 2006.
 
10
F.-L. Yang, J.-R. Hwang, H.-M. Chen, J.-J. Shen, S.-M. Yu, Y. Li, and Denny D. Tang, "Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS," in VLSI Technol. Tech. Symp. Dig., pp. 208--209, June 2007.
 
11
F.-L. Yang, J.-R. Hwang, and Y. Li, "Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices," in IEEE Custom Integrated Circuits Conf., pp. 691--694, Sept. 2006.
 
12
 
13
Y. Li, and C.-H Hwang, "Discrete-dopant-induced characteristic fluctuations in 16 nm multiple-gate siliconon-insulator devices", J. Appl. Phy., vol. 102, no. 8, 084509, 2007.
 
14
Y. Li, and S.-M. Yu, "A Coupled-Simulation-and-Optimization Approach to Nanodevice Fabrication With Minimization of Electrical Characteristics Fluctuation," IEEE Trans. Semi. Manufacturing, vol. 20, no. 4, pp.432--438, Nov. 2007.
 
15
Y. Li, and S.-M. Yu, "A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation," J. Comp. Elect., vol. 5, no. 2--3, pp. 125--129, July 2006.
 
16
A. Asenov, "Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 um MOSFET's: A 3-D "Atomistic" Simulation Study," IEEE Trans. Electron Device, vol. 45, no. 12, pp. 195--200, Dec. 1998.
 
17
A. Asenov and S. Saini, "Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-um MOSFET's with Epitaxial and -Doped Channels," IEEE Trans. Electron Device, vol. 46, no. 8, pp. 1718--1724, Aug. 1999.
 
18
K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, and C. Hu, "A 0.1- m delta doped MOSFET fabricated with post-low-energy implanting selective epitaxy," IEEE Trans. Electron Device, vol. 45, no. 4, pp. 809--813, Apr. 1998.
 
19
G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, "Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs," IEEE Trans. Electron Device, vol. 53, no. 12, pp. 3063--3070, Dec. 2006.
 
20
W. J. Gross, D. Vasileska, and D. K. Ferry," A novel approach for introducing the electron-electron and electron-impurity interactions in particle-based simulations," IEEE Electron Device Letter, vol. 20, no. 9, pp. 463--465, Sept. 1999.
 
21
D. J. Frank, Y. Taur, and H.-S. P. Wong, "Monte Carlo modeling of threshold variation due to dopant fluctuations," in Proc. Symp. VLSI Technology, 1999, pp. 169--170.
 
22
R. Tanabe, Y. Ashizawa, H. Oka, "Investigation of SNM with Random Dopant Fluctuations for FD SGSOI and FinFET 6T SOI SRAM Cell by Three-dimensional Device Simulation," in Simulation of Semiconductor Processes and Device Conf., pp. 103--106, Sept. 2006.
 
23
B. Cheng, S. Roy, G. Roy, and A. Asenov, "Impact of Intrinsic Parameter Fluctuations on SRAM Cell Design," in Int. Solid-State and Integrated Circuit Technology Conf., pp. 1290--1292, Oct. 2006.
 
24
H. Mahmoodi, S. Mukhopadhyay, and K. Roy," Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1787--1796, Sept. 2005.
 
25
B. Cheng, S. Roy, G. Roy, A. Brown, and A. Asenov, "Impact of Random Dopant Fluctuation on Bulk CMOS 6-T SRAM Scaling," in Proc.36th European Solid-State Device Research Conf., pp. 258--261, Sept. 2006.
 
26
A. Brown and A. Asenov, "Capacitance fluctuations in bulk MOSFETs due to random discrete dopants," J. Comp. Elect., Jan. 2008. DOI:10.1007/s10825-008-0181-y.
 
27
S. Odanaka, "Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures," IEEE Trans. Computer-Aided Design Integr. Circuit and Sys., vol. 23, no. 6, pp.837--842, June 2004.
 
28
G. Roy, A. R. Brown, A. Asenov, and S. Roy, "Quantum Aspects of Resolving Discrete Charges in 'Atomistic' Device Simulations," J. Comp. Elect., vol. 2, no. 2--4, pp. 323--327, Dec. 2003.
 
29
 
30
Y. Li, S. M. Sze, and T. S. Chao, "A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation," Eng. with Comp., vol. 18, no. 2, pp. 124--137, Aug., 2002.
 
31
T. Grasser, and S. Selberherr, "Mixed-mode device simulation," Microelectronics Journal, vol. 31, no. 11--12, pp.873--881, Dec. 2000.
 
32
K.-Y. Huang, Y. Li, and C.-P. Lee, "A time-domain approach to simulation and characterization of RF HBT two-tone intermodulation distortion," IEEE Trans. Microwave Theory and Tech., vol.51, no.10, pp.2055--2062, Oct. 2003.
 
33
Y. Li, J.-Y. Huang and B.-S. Lee, "Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors," Semiconductor Science and Technology, vol. 23, 015019, 2008.

Collaborative Colleagues:
Yiming Li: colleagues
Chih-Hong Hwang: colleagues
Ta-Ching Yeh: colleagues
Tien-Yeh Li: colleagues