A framework for predictive dynamic temperature management of microprocessor systems

ABSTRACT

The sustained push for performance, transistor count and instruction level parallelism has reached a point where IC thermal issues are at the forefront of design constraints. Many of the current systems deploy dynamic voltage and frequency scaling (DVFS) to address thermal emergencies. DVFS has certain limitations in terms of response lag, scalability and being reactive. On the other hand, several hardware based control theoretic schemes have been proposed to deliver optimal performance, but such schemes come at high cost and lack flexibility and scalability. In this paper, we present an alternative thermal monitoring and management system that utilizes software and hardware components, based on virtual machine concept. The proposed scheme delivers targeted, localized, and preemptive thermal management at low cost, adapts well to a multitasking environment, while delivering maximum performance under thermal stress.

REFERENCES

• 1: D. Brooks, M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors", ISCA, 2001
• 2: K. Skadron et al., "Temperature-Aware Microarchitecture: Extended Discussion and Results", U. Va., Tech. Report CS-2003-08, 2003
• 3: E. Rohou, M. Smith, "Dynamically managing processor temperature and power", In 2nd Workshop on Feedback Directed Optimization, Nov. 1999
• 4: Jayanth Srinivasan , Sarita V. Adve, Predictive dynamic thermal management for multimedia applications, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA [doi>10.1145/782814.782831]
• 5: T. D. Burd, T. Pering, A. Stratakos, R. Broderson, "Dynamic Voltage Scaled Microprocessor System", ISSCC, Vol. 35, No. 11, Nov. 2000
• 6: Advanced Configuration and Power Interface (ACPI). Document available at http://www.acpi.info/spec.htm
• 7: "Revision Guide for AMD NPT Family 0Fh Processors", AMD Publication # 33610, October 2006, Page 13
• 8: C. Poirier, R. McGowen, C. Bostak, S. Naffziger, "Power and Temperature Control on a 90nm Itanium®-Family Processor", ISSCC, 2005
• 9: International Technology Roadmap for Semiconductor (ITRS). Document available at http://public/itrs.net/
• 10: M. Kanellos, "Intel's roadmap quickly reworked", CNET News.com, May 2004
• 11: Hector Sanchez , Belli Kuttanna , Tim Olson , Mike Alexander , Gian Gerosa , Ross Philip , Jose Alvarez, Thermal Management System for High Performance PowerPCTM Microprocessors, Proceedings of the 42nd IEEE International Computer Conference, p.325, February 23-26, 1997
• 12: Michael Huang , Jose Renau , Seung-Moon Yoo , Josep Torrellas, A framework for dynamic energy efficiency and temperature management, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.202-213, December 2000, Monterey, California, United States [doi>10.1145/360128.360149]
• 13: Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
• 14: Jim Smith , Ravi Nair, Virtual Machines: Versatile Platforms for Systems and Processes (The Morgan Kaufmann Series in Computer Architecture and Design), Morgan Kaufmann Publishers Inc., San Francisco, CA, 2005
• 15: J. Renau et al., "SESC Simulator", 2005; http://sesc.sourceforge.net
• 16: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 17: P. Shivakumar, N. Jouppi, "CACTI 3.0: An integrated cache timing, power, and area model", Tech. Report 2001/2, Compaq, 2001
• 18: K. Skadron et al., "HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level", In THERMINIC, 2002