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Pyramids: an efficient computational geometry-based approach for timing-driven placement
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International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents
San Jose, California
SESSION: Placement table of contents
Pages 204-211  
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
Authors
Tao Luo  Magma Design Automation, Austin, TX and University of Texas at Austin, Austin, TX
David A. Papa  University of Michigan, Ann Arbor, MI and IBM Austin Research Lab, Austin, TX
Zhuo Li  IBM Austin Research Lab, Austin, TX
C. N. Sze  IBM Austin Research Lab, Austin, TX
Charles J. Alpert  IBM Austin Research Lab, Austin, TX
David Z. Pan  University of Texas at Austin, Austin, TX
Sponsors
: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 39,   Citation Count: 0
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ABSTRACT

The purpose of global placement is to find non-overlapping locations for cells, typically while minimizing a wirelength objective. Because of this objective, however, when more timing information about the design is known, some cells will inevitably be sub-optimally placed from a timing perspective. In this paper, we present two new techniques to incrementally improve placements by moving cells to their optimal timing locations. We call our approach Pyramids, since it uses pyramid-shaped delay surfaces to solve for the optimal location, rather than running a more expensive linear programming solver. We show how to apply these techniques to timing-driven detailed placement and also for more accurate latestage incremental timing correction. Experimental results validate the effectiveness of Pyramids by showing significantly improved timing after an industrial placement algorithm. Furthermore, compared to the linear programming solvers, the speedup of Pyramids solver is 373x vs. CLP and 448x vs. GLPK.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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COIN-OR linear programming, "https://projects.coin-or.org/clp,"
 
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GNU Linear Programming Kit, "http://www.gnu.org/software/glpk/,"
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C. J. Alpert and et. al., "Accurate estimation of global buffer delay within a floorplan," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2006.
 
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P. C. P. Saxena, N. Menezes and D. A. Kirkpatrick, "Repeater scaling and its impact on cad," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2004.
 
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OpenAccess, "http://openeda.si2.org/,"
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OAGear:, "http://openedatools.si2.org/oagear/,"
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Collaborative Colleagues:
Tao Luo: colleagues
David A. Papa: colleagues
Zhuo Li: colleagues
C. N. Sze: colleagues
Charles J. Alpert: colleagues
David Z. Pan: colleagues