On capture power-aware test data compression for scan-based testing

ABSTRACT

Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the "don't-care" bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.

REFERENCES

• 1: Kenneth M. Butler , Jayashree Saxena , Tony Fryars , Graham Hetherington, Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques, Proceedings of the International Test Conference on International Test Conference, p.355-364, October 26-28, 2004
• 2: Anshuman Chandra , Krishnendu Chakrabarty, Reduction of SOC test data volume, scan power and testing time using alternating run-length codes, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514090]
• 3: Patrick Girard, Survey of Low-Power Testing of VLSI Circuits, IEEE Design & Test, v.19 n.3, p.82-92, May 2002 [doi>10.1109/MDT.2002.1003802]
• 4: P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici. Variable-length input Huffman coding for system-on-a-chip test. IEEE Transactions on Computer-Aided Design, 22(6):783--796, June 2003.
• 5: Ilker Hamzaoglu , Janak H. Patel, Test set compaction algorithms for combinational circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.283-289, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288615]
• 6: The International Technology Roadmap for Semiconductors (ITRS): 2001 Edition. http://public.itrs.net/Files/2001ITRS/Home.htm, 2001.
• 7: Jia Li , Qiang Xu , Yu Hu , Xiaowei Li, On reducing both shift and capture power for scan-based testing, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
• 8: Jia Li , Qiang Xu , Yu Hu , Xiaowei Li, iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany [doi>10.1145/1403375.1403663]
• 9: C. C. Krishna , Abhijit Jas , Nur A. Touba, Test vector encoding using partial LFSR reseeding, Proceedings of the IEEE International Test Conference 2001, p.885-893, October 30-November 01, 2001
• 10: J. Rajski, et al. Embedded Deterministic Test. IEEE Transactions on Computer-Aided Design, 23(5):776--792, May 2004.
• 11: S. Remersaro, et al. Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. In Proc. International Test Conference (ITC), paper 32.2, 2006.
• 12: P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici. Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction. IEEE Transactions on Computer-Aided Design, 23(7):1142--1153, October 2004.
• 13: J. Saxena, et al. A Case Study of IR-Drop in Structured At-Speed Testing. In Proc. International Test Conference (ITC), pp. 1098--1104, 2003.
• 14: Nur A. Touba, Survey of Test Vector Compression Techniques, IEEE Design & Test, v.23 n.4, p.294-303, July 2006 [doi>10.1109/MDT.2006.105]
• 15: Z. Wang and K. Chakrabarty. Test data compression for IP embedded cores using selective encoding of scan slices. In Proc. International Test Conference (ITC), pp. 581--590, 2005.
• 16: X. Wen, et al. Low-Capture-Power Test Generation for Scan-Based At-Speed Testing. In Proc. International Test Conference (ITC), pp. 1019--1028, 2005.
• 17: Lee Whetsel, Adapting Scan Architectures for Low Power Operation, Proceedings of the 2000 IEEE International Test Conference, p.863, October 03-05, 2000
• 18: Q. Xu, D. Hu, and D. Xiang. Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction. Proc. International Test Conference (ITC), paper 25.2, 2007.
• 19: J.-L. Yang and Q. Xu. State-Sensitive X-Filling Scheme for Scan Capture Power Reduction. IEEE Transactions on Computer-Aided Design, 27(7):1338--1343, July 2008.