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Boolean factoring and decomposition of logic networks
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International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents
San Jose, California
SESSION: Logic and high-level synthesis table of contents
Pages 38-44  
Year of Publication: 2008
ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5
Authors
Alan Mishchenko  University of California, Berkeley
Robert Brayton  University of California, Berkeley
Satrajit Chatterjee  Intel Corporation, Strategic CAD Labs, Hillsboro, OR
Sponsors
: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
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Downloads (6 Weeks): 11,   Downloads (12 Months): 80,   Citation Count: 2
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ABSTRACT

This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut-based view of a logic network, 2) exploiting the uniqueness and speed of disjoint-support decompositions, 3) a new heuristic for speeding these up, 4) extending these to general decompositions, and 5) limiting local transformations to functions with 16 or less inputs so that fast truth table manipulations can be used in all operations. Boolean methods lessen the structural bias of algebraic methods, while still allowing for high speed and multiple iterations. Experimental results on K-LUT networks show an average additional reduction of 5.4% in LUT count, while preserving delay, compared to heavily optimized versions of the same networks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
Alan Mishchenko: colleagues
Robert Brayton: colleagues
Satrajit Chatterjee: colleagues