Challenges at 45nm and beyond

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Challenges at 45nm and beyond

Source

International Conference on Computer Aided Design archive
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design table of contents

San Jose, California

SESSION: Designer's panel table of contents

Article No. 7

Year of Publication: 2008

ISBN ~ ISSN:1092-3152 , 978-1-4244-2820-5

Authors

Dan Bailey	Advanced Micro Devices, Inc., Austin, TX
Eric Soenen	Taiwan Semiconductor Mfg. Co., Austin, TX
Puneet Gupta	Univ. of California, Los Angeles, CA
Paul Villarrubia	IBM Corp., Austin, TX
Sang Dhong	IBM Corp., Sunnyvale, CA

Sponsors

: IEEE CASS/CANDE
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 0

Additional Information:

abstract collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

ABSTRACT

Design at 45nm technologies and below is a risky proposition because of the many design challenges involved: variability, leakage, verification complexity, poor analog device performance, etc. In this panel, experienced designers coming from different backgrounds talk about how they have overcome some of the design and CAD challenges in 45nm, what CAD challenges still exist and how the CAD community can help.

Collaborative Colleagues:

Dan Bailey: colleagues

Eric Soenen: colleagues

Puneet Gupta: colleagues

Paul Villarrubia: colleagues

Sang Dhong: colleagues

Adobe Acrobat

QuickTime

Windows Media Player

Real Player