Nanolithography and CAD challenges for 32nm/22nm and beyond

ABSTRACT

The semiconductor industry is stuck at 193nm lithography as the main workhorse for manufacturing integrated circuits of 45nm and most likely 32nm nodes. On one hand, many novel approaches are being developed to extend the 193nm lithography, including immersion, double patterning, and exotic resolution enhancement techniques. On the other hand, next generation lithography, in particular, extreme ultra violet lithography (EUVL) is projected by ITRS as the main contender for technology nodes at or below 22nm, though significant challenges still exist from both technology and economy aspects. This tutorial will cover key nanolithography and CAD challenges with possible solutions for 32nm/22nm (and beyond?), from the underlying hardware/equipment perspectives (for double patterning, EUV, and so on), to the computational lithography aspects (extreme RET, inverse lithography, pixelated mask, etc.), and to the key EDA issues on nanolithofriendly layouts (e.g., double patterning compliance layout, and so on).