A novel BIST approach for testing input/output buffers in FPGAs

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A novel BIST approach for testing input/output buffers in FPGAs

Source

International Symposium on Field Programmable Gate Arrays archive
Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays table of contents

Monterey, California, USA

POSTER SESSION: Architectures & applications table of contents

Pages 285-285

Year of Publication: 2009

ISBN:978-1-60558-410-2

Authors

Chen Lei	Beijing Microelectronics Technology Institution, Beijing, China
Zhang Zhi Quan	Beijing Microelectronics Technology Institution, Beijing, China
Wen Zhi Ping	Beijing Microelectronics Technology Institution, Beijing, China

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

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Additional Information:

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ABSTRACT

A novel Built-In Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series FPGAs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been successfully implemented and verified on Xilinx Virtex series FPGA. Only total of eight configurations are required to completely built-in self test of the I/O buffers in Virtex series FPGA.

INDEX TERMS

Primary Classification:
B. Hardware
B.2 ARITHMETIC AND LOGIC STRUCTURES
B.2.3 Reliability, Testing, and Fault-Tolerance**