The input-aware dynamic adaptation of area and performance for reconfigurable accelerator

ABSTRACT

Attaching reconfigurable loop accelerator to a processor is a promising way to improve the performance and efficiency of the system. It's usually to unroll a loop to increase the parallelism of a loop accelerator. While the higher degree a loop is unrolled, the more reconfigurable area is needed. However, an observation is that the utilization of the loop accelerator is relative to the input. Focusing on the area and performance balance, a dynamically adaptive reconfigurable accelerator framework is proposed on CPU/RA architecture in the paper. Firstly, the inputs are classified into certain predefined types. At run-time the input of the application will be monitored and then the accelerator will be reconfigured to accomplish the area-performance dynamic adaption. An accelerator selection model is also presented to choose an accelerator at run-time according to the predefined input types. And a bzip2 case study is presented, the experimental results demonstrated the feasibility of the approach, and shown that up to 93.6% reconfigurable area is saved at a cost of 1.6% performance lost in a best case.

REFERENCES

• 1: Paul Chow , Mike Hutton, Integrating FPGAs in high-performance computing: introduction, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA [doi>10.1145/1216919.1216940]
• 2: Intel® QuickAssist Technology Overview. http://www.intel.com/technology/platforms/quickassist/index.htm, 2008-05-09
• 3: Intel Corp. Intel® QuickAssist Technology White Paper. 2007.
• 4: Intel Corp. Intel® QuickAssist Technology Accelerator Abstraction Layer (AAL) White Paper. 2007.
• 5: Xilinx Inc., Virtex-5 Family Overview LX, LXT, and SXT Platforms, 2007.
• 6: Bzip2 homepage, http://www.bzip.org/.
• 7: Seng Lin Shee , Sri Parameswaran , Newton Cheung, Novel architecture for loop acceleration: a case study, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA [doi>10.1145/1084834.1084908]
• 8: A. J. Elbirt , C. Paar, An FPGA implementation and performance evaluation of the Serpent block cipher, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.33-40, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329176]
• 9: Hea Joung Kim , William H. Mangione-Smith, Factoring large numbers with programmable hardware, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.41-48, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329177]
• 10: J. R. Hauser , J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.12, April 16-18, 1997
• 11: K. H. Leung , K. W. Ma , W. K. Wong , P. H. W. Leong, FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.68, April 17-19, 2000
• 12: M. Rencher , B. L. Hutchings, Automated target recognition on SPLASH 2, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.192, April 16-18, 1997
• 13: Markus Weinhardt , Wayne Luk, Pipeline Vectorization for Reconfigurable Systems, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.52, April 21-23, 1999
• 14: Lorenz Huelsbergen, A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.105-115, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329190]
• 15: P. Zhong , M. Martonosi , P. Ashar , S. Malik, Accelerating Boolean Satisfiability with Configurable Hardware, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.186, April 15-17, 1998
• 16: Wei-Je Huang , Nirmal Saxena , Edward J. McCluskey, A Reliable LZ Data Compressor on Reconfigurable Coprocessors, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.249, April 17-19, 2000
• 17: Nicholas Weaver , Vern Paxson , Jose M. Gonzalez, The shunt: an FPGA-based accelerator for network intrusion prevention, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA [doi>10.1145/1216919.1216952]
• 18: Tim Gueneysu , Christof Paar , Jan Pelzl, Attacking elliptic curve cryptosystems with special-purpose hardware, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA [doi>10.1145/1216919.1216953]
• 19: Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002 [doi>10.1145/508352.508353]
• 20: D. C. Cronquist , P. Franklin , S. G. Berg , C. Ebeling, Specifying and Compiling Applications for RaPiD, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.116, April 15-17, 1998
• 21: Silviu Ciricescu , Ray Essick , Brian Lucas , Phil May , Kent Moat , Jim Norris , Michael Schuette , Ali Saidi, The Reconfigurable Streaming Vector Processor (RSVPTM), Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.141, December 03-05, 2003
• 22: Binu Mathew , Al Davis, A loop accelerator for low power embedded VLIW processors, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden [doi>10.1145/1016720.1016726]
• 23: Kevin Fan , Manjunath Kudlur , Hyunchul Park , Scott Mahlke, Increasing hardware efficiency with multifunction loop accelerators, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea [doi>10.1145/1176254.1176322]
• 24: Nathan Clark , Amir Hormati , Scott Mahlke, VEAL: Virtualized Execution Accelerator for Loops, Proceedings of the 35th International Symposium on Computer Architecture, p.389-400, June 21-25, 2008
• 25: Seng Lin Sheey, Sri Parameswarany and Newton Cheungz. Novel Architecture for Loop Acceleration: A Case Study.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.0 General

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

General Terms:
Design, Experimentation, Performance

Keywords:
dynamic adaption, loop accelerator, loop unrolling, reconfigurable system