An intermediate hardware model with load/store unit for C to FPGA

ABSTRACT

We propose the semi-programmable hardware (SPHW) as an intermediate hardware that can be used by the designers and the high-level synthesis tools converting the C programs to FPGAs. The SPHW consists of a load/store unit (LSU), a reconfigurable register file (RRF) and an execution unit (EXU). The LSU, executing the load/store instructions, transfers the data between the memory and the RRF. The hardware designed to make the computation faster is implemented on the EXU. The EXU is a reconfigurable hardware unit and processes the data on the RRF. The LSU flexibly performs complex memory accesses and bufferings by programming, so that the EXU can uniformly process the sequential data on the RRF. Since the EXU runs in parallel to the LSU, the memory access can be overlapped with the data processing. In addition, the SPHW that has a synchronization mechanism supports an execution of the multiple hardware threads on the EXU. By using the SPHW, the C programs can be easily converted to the hardware modules with data prefetching mechanisms. An experiment is performed using some application programs that show different memory access patterns. Compared with the cases that the custom data prefetching circuit is attached instead of the LSU, the SPHW can significantly reduce a design cost, achieving a comparable performance.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids

General Terms:
Design, Performance, Verification

Keywords:
buffering, design method, fpga., memory