Automatic bus macro placement for partially reconfigurable FPGA designs

ABSTRACT

Dynamic Partial Reconfiguration of FPGAs partitions the configurable logic fabric into static and reconfigurable regions. The reconfigurable regions' functionality changes at run time while the static regions continue unperturbed. The reconfigurable and static regions interface via fixed connection points ("bus macros"). We introduce the notion of a fitness score as the measure of how well the combined designs meet their timing constraints, subject to a given bus macro placement. We present a tool that uses design-space exploration to obtain automatic, near-optimal placements. The tool achieves 76% better fitness scores over manual placements. The location of the bus macros around a region has a noticeable impact on the timings, and we found that this is accurately reflected on our fitness score. We also found that following the accepted best design practices leads to quantifiably sub-optimal placements, underscoring the need for such a tool.

REFERENCES

• 1: http://xilinx.com/support/prealounge/protected/index.htm
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Design, Performance

Keywords:
dynamic partial reconfiguration, emips, floor-planning, reconfigurable computing