Flexible multi-mode embedded floating-point unit for field programmable gate arrays

ABSTRACT

Performance of Field Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. This makes FPGAs less attractive for use in floating-point intensive applications. Therefore, there is a need for embedded floating-point units (FPUs) in FPGAs. However, if unutilized, embedded FPUs waste space on the FPGA die. To overcome this issue, we propose a flexible multi-mode embedded FPU for FPGAs that can be configured to perform a wide range of operations. The floating-point adder and multiplier in our embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on our FPGA with embedded FPU blocks. The results using our embedded FPUs showed a mean area improvement of 5.2 times and a mean delay improvement of 5.8 times for the double-precision benchmarks, and a mean area improvement of 4.4 times and a mean delay improvement of 4.2 times for the single-precision benchmarks.

REFERENCES

• 1: Michael J. Beauchamp , Scott Hauck , Keith D. Underwood , K. Scott Hemmert, Embedded floating-point units in FPGAs, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA [doi>10.1145/1117201.1117204]
• 2: C. H. Ho , P. H. W. Leong , W. Luk , S. J. E. Wilton , S. Lopez-Buedo, Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs, Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.35-44, April 24-26, 2006 [doi>10.1109/FCCM.2006.71]
• 3: C.H. Ho, C.W. Yu, P.H.W. Leong, W. Luk, and S.J.E. Wilton. Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. In International Conference on Field Programmable Logic and Applications (FPL 2007), pages 196--201, August 2007.
• 4: Hard vs. Soft: The Central Question of Pre-Fabricated Silicon, Proceedings of the 34th International Symposium on Multiple-Valued Logic, p.2-5, May 19-22, 2004
• 5: Ahmet Akkas, Dual-Mode Quadruple Precision Floating-Point Adder, Proceedings of the 9th EUROMICRO Conference on Digital System Design, p.211-220, August 30-September 01, 2006 [doi>10.1109/DSD.2006.47]
• 6: Guy Even , Silvia M. Mueller , Peter-Michael Seidel, A dual precision IEEE floating-point multiplier, Integration, the VLSI Journal, v.29 n.2, p.167-180, Sept. 2000 [doi>10.1016/S0167-9260(00)00006-7]
• 7: Ahmet Akkas , Michael J. Schulte, A Quadruple Precision and Dual Double Precision Floating-Point Multiplier, Proceedings of the Euromicro Symposium on Digital Systems Design, p.76, September 01-06, 2003
• 8: P.C. Diniz and G. Govindu. Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit. In International Conference on Field Programmable Logic and Applications (FPL'06), pages 1--4, August 2006.
• 9: IEEE standard for binary floating-point arithmetic, 1985.
• 10: David A. Patterson , John Hennessy, Computer Organization and Design, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2004
• 11: V.G. Oklobdzija. An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1):124--128, March 1994.
• 12: H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko, and T. Sumi. Leading-zero anticipatory logic for high speed floating-point addition. IEEE Journal of Solid-State Circuits, 31(8):157--1164, 1996.
• 13: Paul Michael Farmwald, On the design of high performance digital arithmetic units, Stanford University, Stanford, CA, 1981
• 14: Michael Nicolaidis , Ricardo O. Duarte, Fault-Secure Parity Prediction Booth Multipliers, IEEE Design & Test, v.16 n.3, p.90-101, July 1999 [doi>10.1109/54.785842]
• 15: Wen-Chang Yeh , Chein-Wei Jen, High-Speed Booth Encoded Parallel Multiplier Design, IEEE Transactions on Computers, v.49 n.7, p.692-701, July 2000 [doi>10.1109/12.863039]
• 16: J.A. Hidalgo, V. Morena-Vegara, O. Oballe, and A.Ü Gago A.ÜDaza, M.J. Martin-Vázquez. A Radix-8 Multiplier Unit Design for Specific Purpose. In XIII Conference of Design of Circuits and Integrated Systems, 1998.
• 17: A.D. Booth. A signed binary multiplication technique. Quarterly J. Mechanical and Applied Math, 4:236--240, 1951.
• 18: H. Sam , A. Gupta, A Generalized Multibit Recoding of Two's Complement Binary Numbers and its Proof with Application in Multiplier Implementations, IEEE Transactions on Computers, v.39 n.8, p.1006-1015, August 1990 [doi>10.1109/12.57039]
• 19: C.S. Wallace. A suggestion for a fast multiplier. IEEE Transactions on Electronic Computers, EC-13:14--17, February 1964.
• 20: Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.0 General

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

General Terms:
Design, Performance

Keywords:
dual-precision, embedded block, floating-point, fpga, fpga architecture, fpu