|
ABSTRACT
Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architecture known as FPCNA. We define novel CNT and nanoswitch based components and characterize these components considering nano-specific process variations, including the variation caused by the random mixture of metallic and semiconducting CNTs. To evaluate the architecture, we develop a variation-aware physical-design flow which can handle both Gaussian and non-Gaussian random variables using variation-aware placement and routing. When FPCNA is evaluated with this CAD flow, we see a 2.67× performance gain over a baseline CMOS FPGA at the same technology node (at a 95% performance yield). In addition, FPCNA offers a 4.5× footprint reduction compared to the baseline FPGA. These results demonstrate the potential of using CNTs and nanoswitches to build high performance FPGA circuits.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
E. Ahmed and J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," IEEE Trans. on VLSI, Vol 12, No. 3, pp. 288--298, March 2004.
|
| |
2
|
|
| |
3
|
|
 |
4
|
|
| |
5
|
J. Deng, et al., "Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections," International Solid-State Circuits Conference, 2007.
|
| |
6
|
C. Dong, D. Chen, S. Haruehanroengra, and W. Wang, "3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits," IEEE Transactions on Circuits and Systems I, Vol. 54, Issue 11, pp. 2489--2501, Nov. 2007.
|
 |
7
|
|
 |
8
|
|
| |
9
|
A. Hassanien, et al., "Selective Etching of Metallic Single-Wall Carbon Nanotubes with Hydrogen Plasma," Nanotechnology, Vol. 16, pp. 278--281, 2005.
|
| |
10
|
S. Kaeriyama, et al., "A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch", IEEE Journal of Solid-State Circuits, Vol.40, No.1, pp. 168--176, Jan. 2005.
|
| |
11
|
S. J. Kang, et al., "High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes," Nature Nanotechnology, Vol. 2, Issue 4, pp. 230--236, 2007.
|
| |
12
|
Y. Li, et al., "Preferential Growth of Semiconducting Single-Walled Carbon Nanotubes by a Plasma Enhanced CVD Method," Nano Letters, vol. 4, pp. 317, 2004.
|
| |
13
|
X. Liu, S. Han, and C. Zhou, "Novel Nanotube-on-Insulator (NOI) Approach toward Single-Walled Carbon Nanotube Devices," Nano Lett. (Letter), 6(1), pp 34--39, 2006.
|
 |
14
|
|
| |
15
|
P. McEuen, M. Fuhrer, and H. Park, "Single-Walled Carbon Nanotube Electronics," Tran. on Nanotechnology, Vol. 1, No. 1, Mar. 2002.
|
 |
16
|
|
| |
17
|
A. Raychowdhury, S. Mukhopadhyay, and K. Roy, "A Circuit-Compatible Model of Ballistic Carbon Nanotube Field-Effect Transistors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 1411--1420, 2004
|
| |
18
|
E. M. Sentovich et. al. "SIS: A System for Sequential Circuit Synthesis," Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, 1992.
|
| |
19
|
G. Snider and S. Williams, "Nano/CMOS architecture using a field-programmable nanowire interconnect," Nanotechnology, vol. 18, 2007.
|
| |
20
|
G. Snider, P. Kuekes, and R. S. Williams, "CMOS-like logic in defective nanoscale crossbars," Nanotechnology, vol. 15, 2004.
|
| |
21
|
|
| |
22
|
D. B. Strukov and K. K. Likharev, "CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, no. 888--900, 2005.
|
| |
23
|
B. Q. Wei, R. Vajtai, and P. M. Ajayan, "Reliability and Current Carrying Capacity of Carbon Nanotubes," Applied Physics Letter, vol. 79, no. 8, pp. 1172--1174, 2001.
|
 |
24
|
|
 |
25
|
|
| |
26
|
NRAMTM, Nantero, http://www.nantero.com/tech.html.
|
| |
27
|
J.W. Ward, M. Meinhold, B.M. Segal, J. Berg, R. Sen, R. Sivarajan, D.K. Brock, T. Rueckes, "A nonvolatile nanoelectromechanical memory element utilizing a fabric of carbon nanotubes," Non-Volatile Memory Technology Symposium, 2004, vol., no., pp. 34--38, 15-17 Nov. 2004
|
| |
28
|
N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, "Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures," 2008 Symp. VLSI Technology, 2008.
|
 |
29
|
|
| |
30
|
Carbon Nanotubes http://phycomp.technion.ac.il/~talimu/structure.html
|
| |
31
|
D. Boning, S. Nassif, "Models of Process Variations in Device and Interconnect," Design of High-Perfromance Microprocessor Circuits, Wiley-IEEE Press, ISBN: 978-0-7803-6001-3, 2000.
|
| |
32
|
|
 |
33
|
Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States
[doi> 10.1145/378239.379043]
|
 |
34
|
C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996663]
|
| |
35
|
S. J. Kang, C. Kocabas, H. S. Kim, Q. Cao, M.A. Meitl, D. Y. Khang, and J.A. Rogers, "Printed multilayer superstructures of aligned single-walled carbon nanotubes for electronic applications," Nano Letters, v 7, n 11, Nov. 2007, p 3343--3348.
|
| |
36
|
E. Pop, "The role of electrical and thermal contact resistance for Joule breakdown of single-wall carbon nanotube," Nanotechnology, v 19, n 29, 23 July 2008, p 295202 (5 pp.)
|
| |
37
|
Y. Lin, M. Hutton, L. He, "Placement and Timing for FPGAs Considering Variations," Field Programmable Logic and Applications, 2006. FPL '06. International Conference on., vol., no., pp.1--7, 28-30 Aug. 2006
|
| |
38
|
International Technology Roadmap for Semiconductors, http://www.itrs.net/.
|
|