Making good points

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Making good points: application-specific pareto-point generation for design space exploration using statistical methods

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International Symposium on Field Programmable Gate Arrays archive
Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays table of contents

Monterey, California, USA

SESSION: CAD tools 2 table of contents

Pages 123-132

Year of Publication: 2009

ISBN:978-1-60558-410-2

Authors

David Sheldon	University of California, Riverside, Riverside, CA, USA
Frank Vahid	University of California, Riverside, Riverside, CA, USA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

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ABSTRACT

Field-programmable gate arrays (FPGAs) commonly implement system architectures composed from soft-core configurable components, such as a cache with configurable size or associativity, a processor with configurable datapath units, or a configurable network-on-chip connecting dozens of processors. Configurable components increasingly exist even on pre-fabricated platforms. Tuning configurable components to the particular application running on the architecture and to particular design constraints represents a challenging task often left to a designer. Knowledge of the Pareto-optimal points of a system for particular applications can be of benefit to designers seeking to make appropriate design tradeoffs for given constraints. Previous methods for generating Pareto points required extensive knowledge of an architecture's parameter interdependencies, used a simplistic approach that failed to find many parameters, or used randomized search algorithms that may have long runtimes. We introduce an algorithm for finding Pareto points, based on statistically rigorous methods derived from the Design of Experiments paradigm and extended for the purpose of finding Pareto points. The resulting DoE-based Pareto point Generator, or DPG, algorithm finds thorough Pareto points while running 3 times faster than randomized search algorithms, without requiring designer knowledge of parameter interdependencies--in fact, the approach determines those interdependencies automatically, representing an added bonus. We demonstrate DPG on Platune's configurable processor-bus-cache system-on-chip, Noxim's configurable network-on-chip, and the configurable Microblaze FPGA processor.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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