A comparison of via-programmable gate array logic cell circuits

ABSTRACT

Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufactuing cost, speed, power and area. In this paper, we present a novel VPGA logic cell, the complementary universal logic gate (CULG) which can be used to implement both sequential and combinatorial elements. Its performance is compared with a number of other designs including transmission gate, differential cascode voltage switch with pass gate, and standard cell. The CULG is found to have comparable power-delay product and process variation sensitivity to the other designs while offering the lowest power consumption.

REFERENCES

• 1: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 2: E. J. Brauer, I. Hatirnaz, S. Badel, and Y. Leblebici. Via-programmable expanded universal logic gate in mcml for structured ASIC applications: circuit design. In International Symposium on Circuits and Systems (ISCAS), 2006.
• 3: eASIC. http://www.easic.com, 2008.
• 4: L. Heller, W. Griffin, J. Davis, and N. Thoma. Cascode voltage switch logic: A differential CMOS logic family. Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International, XXVII:16--17, Feb 1984.
• 5: A. Koorapaty , V. Chandra , K. Y. Tong , C. Patel , L. Pileggi , H. Schmit, Heterogeneous Programmable Logic Block Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.11118, March 03-07, 2003
• 6: I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 26(2):203--215, Feb. 2007.
• 7: F. Lai and W. Hwang. Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems. In Proceedings of the International Symposium on VLSI Technology, Systems, and Applications, pages 358--362, 1993.
• 8: Chetan Patel , Anthony Cozzie , Herman Schmit , Larry Pileggi, An architectural exploration of via patterned gate arrays, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640039]
• 9: H. K. Phoon, M. Yap, and C. K. Chai. A highly compatible architecture design for optimum FPGA to structured-ASIC migration. In IEEE International Conference on Semiconductor Electronics (ICSE), pages 506--510, 2006.
• 10: Y. Ran and M. Marek-Sadowska. Designing via-configurable logic blocks for regular fabric. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(1):1--14, Jan 2006.
• 11: K. Y. Tong, V. Kheterpal, V. Rovner, L. Pileggi, H. Schmit, and R. Puri. Regular logic fabrics for a via patterned gate array (VPGA). In Proceedings of the Custom Integrated Circuits Conference, pages 4.3.1--4.3.4, 2003.
• 12: K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu. A 3.8-ns CMOS 16×16-b multiplier using complementary pass-transistor logic. Solid-State Circuits, IEEE Journal of, 25(2):388--395, Apr 1990.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

General Terms:
Design

Keywords:
logic cell, via-programmable gate arrays