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NePalTM: design and implementation of nested parallelism for transactional memory systems
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Principles and Practice of Parallel Programming archive
Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming table of contents
Raleigh, NC, USA
POSTER SESSION: Posters table of contents
Pages 291-292  
Year of Publication: 2009
ISBN:978-1-60558-397-6
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Authors
Haris Volos  University of Wisconsin, Madison, WI, USA
Adam Welc  Intel Corporation, Santa Clara, CA, USA
Ali-Reza Adl-Tabatabai  Intel Corporation, Santa Clara, CA, USA
Tatiana Shpeisman  Intel Corporation, Santa Clara, CA, USA
Xinmin Tian  Intel Corporation, Santa Clara, CA, USA
Ravi Narayanaswamy  Intel Corporation, Santa Clara, CA, USA
Sponsors
ACM: Association for Computing Machinery
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

We present the programming model, design and implementation of NePalTM; a transactional memory system where atomic blocks can be used for concurrency control at an arbitrary level of nested parallelism.


REFERENCES

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Collaborative Colleagues:
Haris Volos: colleagues
Adam Welc: colleagues
Ali-Reza Adl-Tabatabai: colleagues
Tatiana Shpeisman: colleagues
Xinmin Tian: colleagues
Ravi Narayanaswamy: colleagues