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Efficient, portable implementation of asynchronous multi-place programs
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Principles and Practice of Parallel Programming archive
Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming table of contents
Raleigh, NC, USA
SESSION: High end computing software table of contents
Pages 271-282  
Year of Publication: 2009
ISBN:978-1-60558-397-6
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Authors
Ganesh Bikshandi  IBM STG, Bangalore, India
Jose G. Castanos  IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Sreedhar B. Kodali  IBM STG, Bangalore, India
V. Krishna Nandivada  IBM India Research Lab, New Delhi, India
Igor Peshansky  IBM T.J. Watson Research Center, Hawthorne, NY, USA
Vijay A. Saraswat  IBM T.J. Watson Research Center, Hawthorne, NY, USA
Sayantan Sur  IBM T.J. Watson Research Center, Hawthorne, NY, USA
Pradeep Varma  IBM India Research Lab, New Delhi, India
Tong Wen  Interactive Supercomputing, Boston, MA, USA
Sponsors
ACM: Association for Computing Machinery
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

The X10 programming language is organized around the notion of places (an encapsulation of data and activities operating on the data), partitioned global address space (PGAS), and asynchronous computation and communication.

This paper introduces an expressive subset of X10, Flat X10, designed to permit efficient execution across multiple single-threaded places with a simple runtime and without compromising on the productivity of X10. We present the design, implementation and evaluation of a compiler and runtime system for Flat X10. The Flat X10 compiler translates programs into C++ SPMD programs communicating using an active messaging infrastructure. It uses novel techniques to transform explicitly parallel programs into SPMD programs. The runtime system is based on IBM's LAPI (Low-level API) and is easily portable to other libraries such as GASNet and ARMCI.

Our implementation realizes performance comparable to hand-written MPI programs for well-known HPC benchmarks such as Random Access, Stream, and FFT, on a Federation-based cluster of Power5 SMPs (with hundreds of processors) and the Blue Gene (with thousands of processors). Submissions based on the work presented in this paper were co-winners of the 2007 and 2008 HPC Challenge Type II Awards.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
Ganesh Bikshandi: colleagues
Jose G. Castanos: colleagues
Sreedhar B. Kodali: colleagues
V. Krishna Nandivada: colleagues
Igor Peshansky: colleagues
Vijay A. Saraswat: colleagues
Sayantan Sur: colleagues
Pradeep Varma: colleagues
Tong Wen: colleagues